POD: A 3D-integrated broad-purpose acceleration layer

IEEE Micro

Volumn 28, Issue 4, 2008, Pages 28-40

  Woo, Dong Hyuk ^a   Lee, Hsien Hsin S ^a   Fryman, Joshua B ^b   Knies, Allan D ^c   Eng, Marsha ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Intel's Microprocessor Technology Lab

^c INTEL CORPORATION   (United States)

Author keywords

Acceleration; Accelerator architectures; Arrays; Delay; Magnetic cores; Out of order; Pipelines

Indexed keywords

ACCELERATION; ACCELERATOR ARCHITECTURES; ARRAYS; DELAY; MAGNETIC CORES; OUT OF ORDER; PIPELINES;

EID: 53749097461     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2008.58     Document Type: Article

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