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Volumn , Issue , 2011, Pages 503-514

Dynamically specialized datapaths for energy efficient computing

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT-SWITCHED NETWORKS; DATA-PATHS; ENERGY EFFICIENT COMPUTING; ENERGY REDUCTION; EXECUTED INSTRUCTIONS; GENERAL PURPOSE; GEOMETRIC MEAN; HETEROGENEOUS COMPUTATION; OUT-OF-ORDER PROCESSORS; PERFORMANCE IMPROVEMENTS; PROCESSOR PIPELINES; PROGRAMMABLE PROCESSORS; SPECIALIZED HARDWARE; TECHNOLOGY SCALING;

EID: 79955890625     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749755     Document Type: Conference Paper
Times cited : (167)

References (40)
  • 2
    • 78049338046 scopus 로고    scopus 로고
    • The single-chip cloud computer
    • April
    • M. Baron. The single-chip cloud computer. Microprocessor Report, April 2010.
    • (2010) Microprocessor Report
    • Baron, M.1
  • 3
    • 70649115688 scopus 로고    scopus 로고
    • Understanding PARSEC performance on contemporary CMPs
    • Austin, TX
    • M. Bhadauria, V. M.Weaver, and S. A. McKee. Understanding PARSEC performance on contemporary CMPs. In IISWC, 2009, pages 98-107, Austin, TX.
    • (2009) IISWC , pp. 98-107
    • Bhadauria, M.1    Weaver, V.M.2    McKee, S.A.3
  • 4
    • 63549095070 scopus 로고    scopus 로고
    • The parsec benchmark suite: Characterization and architectural implications
    • C. Bienia, S. Kumar, J. P. Singh, and K. Li. The parsec benchmark suite: Characterization and architectural implications. In PACT '08.
    • PACT '08
    • Bienia, C.1    Kumar, S.2    Singh, J.P.3    Li, K.4
  • 7
    • 27544482359 scopus 로고    scopus 로고
    • An architecture framework for transparent instruction set customization in embedded processors
    • N. Clark, J. Blome, M. Chu, S. Mahlke, S. Biles, and K. Flautner. An architecture framework for transparent instruction set customization in embedded processors. In ISCA '05, pages 272-283, 2005.
    • (2005) ISCA '05 , pp. 272-283
    • Clark, N.1    Blome, J.2    Chu, M.3    Mahlke, S.4    Biles, S.5    Flautner, K.6
  • 8
    • 52649095061 scopus 로고    scopus 로고
    • Veal: Virtualized execution accelerator for loops
    • N. Clark, A. Hormati, and S. Mahlke. Veal: Virtualized execution accelerator for loops. In ISCA '08, pages 389-400, 2008.
    • (2008) ISCA '08 , pp. 389-400
    • Clark, N.1    Hormati, A.2    Mahlke, S.3
  • 9
    • 21644435314 scopus 로고    scopus 로고
    • Application-specific processing on a general-purpose core via transparent instruction set customization
    • N. Clark, M. Kudlur, H. Park, S. Mahlke, and K. Flautner. Application-specific processing on a general-purpose core via transparent instruction set customization. In MICRO 37, pages 30-40, 2004.
    • (2004) MICRO 37 , pp. 30-40
    • Clark, N.1    Kudlur, M.2    Park, H.3    Mahlke, S.4    Flautner, K.5
  • 10
    • 0026243790 scopus 로고
    • Efficiently computing static single assignment form and the control dependence graph
    • Oct
    • R. Cytron, J. Ferrante, B. K. Rosen, M. N. Wegman, and F. K. Zadeck. Efficiently computing static single assignment form and the control dependence graph. ACMTOPLAS, 13(4):451-490, Oct 1991.
    • (1991) ACMTOPLAS , vol.13 , Issue.4 , pp. 451-490
    • Cytron, R.1    Ferrante, J.2    Rosen, B.K.3    Wegman, M.N.4    Zadeck, F.K.5
  • 14
    • 70350708988 scopus 로고    scopus 로고
    • Ambric'S New Parallel Processor - Globally Asynchronous Architecture Eases Parallel Programming
    • October
    • T. R. Halfhill. Ambric'S New Parallel Processor - Globally Asynchronous Architecture Eases Parallel Programming. Microprocessor Report, October 2006.
    • (2006) Microprocessor Report
    • Halfhill, T.R.1
  • 15
    • 79955922294 scopus 로고    scopus 로고
    • MathStar Challenges FPGAs
    • July
    • T. R. Halfill. MathStar Challenges FPGAs. Microprocessor Report, 20(7):29-35, July 2006.
    • (2006) Microprocessor Report , vol.20 , Issue.7 , pp. 29-35
    • Halfill, T.R.1
  • 19
    • 40349103955 scopus 로고    scopus 로고
    • Memory prefetching using adaptive stream detection
    • I. Hur and C. Lin. Memory prefetching using adaptive stream detection. In MICRO 39, pages 397-408.
    • MICRO 39 , pp. 397-408
    • Hur, I.1    Lin, C.2
  • 21
    • 0036949290 scopus 로고    scopus 로고
    • Design and evaluation of compiler algorithms for pre-execution
    • DOI 10.1145/635508.605415
    • D. Kim and D. Yeung. Design and evaluation of compiler algorithms for pre-execution. SIGPLAN Not., 37(10):159-170, 2002. (Pubitemid 44892231)
    • (2002) Operating Systems Review (ACM) , vol.36 , Issue.5 , pp. 159-170
    • Kim, D.1    Yeung, D.2
  • 22
    • 0020126847 scopus 로고
    • The burroughs scientific processor (bsp)
    • May
    • D. J. Kuck and R. A. Stokes. The burroughs scientific processor (bsp). IEEE Trans. Comput., 31:363-376, May 1982.
    • (1982) IEEE Trans. Comput. , vol.31 , pp. 363-376
    • Kuck, D.J.1    Stokes, R.A.2
  • 23
    • 3042658703 scopus 로고    scopus 로고
    • LLVM: A compilation framework for life-long program analysis & transformation
    • C. Lattner and V. Adve. LLVM: A compilation framework for life-long program analysis & transformation. In CGO '04, pages 75-88.
    • CGO '04 , pp. 75-88
    • Lattner, C.1    Adve, V.2
  • 25
    • 0026980852 scopus 로고    scopus 로고
    • Effective compiler support for predicated execution using the hyperblock
    • S. Mahlke, D. Lin, W. Chen, R. Hank, and R. Bringmann. Effective compiler support for predicated execution using the hyperblock. In ISCA '92, pages 45-54.
    • ISCA '92 , pp. 45-54
    • Mahlke, S.1    Lin, D.2    Chen, W.3    Hank, R.4    Bringmann, R.5
  • 28
    • 16244399540 scopus 로고    scopus 로고
    • A loop accelerator for low power embedded vliw processors
    • B. Mathew and A. Davis. A loop accelerator for low power embedded vliw processors. In CODES+ISSS '04, pages 6-11.
    • CODES+ISSS '04 , pp. 6-11
    • Mathew, B.1    Davis, A.2
  • 32
    • 85046463637 scopus 로고
    • Decoupled access/execute computer architectures
    • J. E. Smith. Decoupled access/execute computer architectures. In ISCA '82, pages 112-119, 1982.
    • (1982) ISCA '82 , pp. 112-119
    • Smith, J.E.1
  • 33
    • 79955919759 scopus 로고    scopus 로고
    • SPEC CPU2006, Standard Performance Evaluation Corporation
    • SPEC CPU2006, Standard Performance Evaluation Corporation.
  • 35
    • 40349106434 scopus 로고    scopus 로고
    • Fire-and-forget: Load/store scheduling with no store queue at all
    • S. Subramaniam and G. H. Loh. Fire-and-forget: Load/store scheduling with no store queue at all. In MICRO 39, pages 273-284, 2006.
    • (2006) MICRO 39 , pp. 273-284
    • Subramaniam, S.1    Loh, G.H.2
  • 37
    • 0036505033 scopus 로고    scopus 로고
    • The RAWMicroprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
    • March
    • M. B. Taylor et al. The RAWMicroprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs, IEEE Micro, 22(2):25-35, March, 2002.
    • (2002) IEEE Micro , vol.22 , Issue.2 , pp. 25-35
    • Taylor, M.B.1
  • 39
    • 0033703884 scopus 로고    scopus 로고
    • Chimaera: A high-performance architecture with a tightly-coupled reconfigurable functional unit
    • Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee. Chimaera: a high-performance architecture with a tightly-coupled reconfigurable functional unit. In ISCA '00, pages 225-235.
    • ISCA '00 , pp. 225-235
    • Ye, Z.A.1    Moshovos, A.2    Hauck, S.3    Banerjee, P.4
  • 40
    • 0033707298 scopus 로고    scopus 로고
    • Understanding the backward slices of performance degrading instructions
    • C. B. Zilles and G. S. Sohi. Understanding the backward slices of performance degrading instructions. In ISCA '00, pages 172-181.
    • ISCA '00 , pp. 172-181
    • Zilles, C.B.1    Sohi, G.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.