1-Tbyte/s 1-Gbit DRAM architecture using 3-D interconnect for high-throughput computing

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 4, 2011, Pages 828-837

  Sekiguchi, Tomonori ^a   Ono, Kazuo ^b   Kotabe, Akira ^b   Yanagawa, Yoshimitsu ^b  

^a Hitachi Europe Ltd   (United Kingdom)

^b HITACHI LTD   (Japan)

Author keywords

3D inter connect; DRAM; multi core; pipeline; TSV

Indexed keywords

3-D INTERCONNECTS; CHIP SIZES; DATA BUS; DRAM; EMBEDDED DRAM; HIGH-THROUGHPUT COMPUTING; INTER-CONNECTS; LOW NOISE; MEMORY ARRAY; MEMORY BOTTLENECK; MEMORY CELL; MEMORY CORE; MULTI CORE; MULTI-CORE SYSTEMS; MULTICORE ARCHITECTURES; OPERATION CYCLES; ORDER OF MAGNITUDE; PARASITIC CAPACITANCE; PIPELINED ARCHITECTURE; POWER CONSUMPTION; POWER EFFICIENCY; STAND -ALONE; THROUGH-SILICON-VIA; TSV;

BUSES; CIRCUIT SIMULATION; MEMORY ARCHITECTURE; THREE DIMENSIONAL; VLSI CIRCUITS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 79953177459     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2109630     Document Type: Article

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