A 1.2V 23nm 6F 2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 42-43

  Lim, Kyu Nam ^a   Jang, Woong Ju ^a   Won, Hyung Sik ^a   Lee, Kang Yeol ^a   Kim, Hyungsoo ^a   Kim, Dong Whee ^a   Cho, Mi Hyun ^a   Kim, Seung Lo ^a   Kang, Jong Ho ^a   Park, Keun Woo ^a   Jeong, Byung Tae ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY ARCHITECTURE; BIT LINES; CLOCK FREQUENCY; COMMON GROUND; DIE AREA; LOW VOLTAGES; READ OPERATION; SENSE AMPLIFIER; SENSING SCHEMES;

EID: 84860674864     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176870     Document Type: Conference Paper

References (5)

1. Satoru Akiyama, Tomonori Sekiguchi, et al., "Low-Vt Small-Offset Gated Preamplifier for Sub-1V Gigabit DRAM Arrays", ISSCC Dig. Tech. Papers, pp. 141-142, Feb. 2009.
2. Amith Singhee and Rob Rutenbar, "Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design", IEEE Trans. CAD of Integrated Circuits and Systems, pp. 1176-1189, vol. 28, no. 8, Aug. 2009.
3. Yongsam Moon, Yong-Ho Cho, et al., "1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with Hybrid-I/O Sense Amplifier and Segmented Sub-Array Architecture", ISSCC Dig. Tech. Papers, pp.128-129, Feb. 2009.
4. Changsik Yoo, Kye-Hyun Kyung, et al., "A 1.8-V 700-Mb/s/pin 512-Mb DDRII SDRAM With On-Die Termination and Off-Chip Driver Calibration", IEEE J. Solid-State Circuits, vol. 39, no. 6, June 2004.
5. 2 Open-Bit-line Cell Distributed Over-Driven Sensing and Stacked-Flash Fuse", ISSCC Dig. Tech. Papers, pp. 380-381, Feb. 2001.