Triggered instructions: A control paradigm for spatially-programmed architectures

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 142-153

  Parashar, Angshuman ^a   Pellauer, Michael ^a   Adler, Michael ^a   Ahsan, Bushra ^a   Crago, Neal ^a   Lustig, Daniel ^d   Pavlov, Vladimir ^b   Zhai, Antonia ^a,e   Gambhir, Mohit ^a   Jaleel, Aamer ^a   Allmon, Randy ^a   Rayess, Rachid ^a   Maresh, Stephen ^b   Emer, Joel ^a,c  

^a VSSAD   (United States)

^b INTEL CORPORATION   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d PRINCETON UNIVERSITY   (United States)

^e UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Reconfigurable accelerators; Spatial programming

Indexed keywords

BRANCH INSTRUCTIONS; DYNAMIC INSTRUCTIONS; GENERAL PURPOSE PROCESSORS; HARDWARE MECHANISM; PROCESSING ELEMENTS; RECONFIGURABLE; SPATIAL PARALLELISM; SPATIAL PROGRAMMING;

CONCURRENCY CONTROL; GENERAL PURPOSE COMPUTERS;

COMPUTER ARCHITECTURE;

EID: 84881163269     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485935     Document Type: Conference Paper

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