A 1.2 v 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 × 128 I/Os using TSV Based Stacking

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 1, 2012, Pages 107-116

  Kim, Jung Sik ^a   Oh, Chi Sung ^a   Lee, Hocheol ^a   Lee, Donghyuk ^a   Hwang, Hyong Ryol ^a   Hwang, Sooman ^a   Na, Byongwook ^a   Moon, Joungwook ^a   Kim, Jin Guk ^a   Park, Hanna ^a   Ryu, Jang Woo ^a   Park, Kiwon ^a   Kang, Sang Kyu ^a   Kim, So Young ^a   Kim, Hoyoung ^a   Bang, Jong Min ^a   Cho, Hyunyoon ^a   Jang, Minsoo ^a   Han, Cheolmin ^a   Lee, Jung Bae ^a   Choi, Joo Sun ^a   Jun, Young Hyun ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

CMOS memory integrated circuits; DRAM chips; through silicon vias

Indexed keywords

BLOCK BASED; CHIP SIZES; CMOS MEMORY INTEGRATED CIRCUITS; DATA BANDWIDTH; DRAM CHIPS; MICRO-BUMPS; OPERATING POWER; TEST CORRELATION; THROUGH SILICON VIAS;

CMOS INTEGRATED CIRCUITS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84655163339     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2164731     Document Type: Article

References (9)

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