Flexible and efficient instruction-grained run-time monitoring using on-chip reconfigurable fabric

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 137-148

  Deng, Daniel Y ^a   Lo, Daniel ^a   Malysa, Greg ^a   Schneider, Skyler ^a   Suh, G Edward ^a  

^a Department of Obstetrics Gynecology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-LEVEL OPERATIONS; CUSTOM HARDWARES; DYNAMIC INFORMATION FLOW TRACKING; MODERN MICROPROCESSOR; ON CHIPS; PROCESSING CORE; PROCESSOR ARCHITECTURES; RECONFIGURABLE ARCHITECTURE; RECONFIGURABLE FABRICS; RUNTIME MONITORING; SILICON AREA; SOFT ERROR; SOFTWARE IMPLEMENTATION; TIGHTLY-COUPLED;

CLOSED LOOP CONTROL SYSTEMS; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; RECONFIGURABLE HARDWARE;

MONITORING;

EID: 79951706157     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.17     Document Type: Conference Paper

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