Garp: a MIPS processor with a reconfigurable coprocessor

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1997, Pages 12-21

  Hauser, John R ^a   Wawrzynek, John ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUFFER STORAGE; COMPUTER HARDWARE; GENERAL PURPOSE COMPUTERS; LOGIC CIRCUITS; RESPONSE TIME (COMPUTER SYSTEMS);

FIELD PROGRAMMABLE GATE ARRAY; GARP ARCHITECTURE; MIPS PROCESSOR; RECONFIGURABLE ARRAY;

COMPUTER ARCHITECTURE;

EID: 0031360911     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)