Reducing memory access latency with asymmetric DRAM bank organizations

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 380-391

  Son, Young Hoon ^a   Seongil, O ^a   Ro, Yuhwan ^a   Lee, Jae W ^b   Ahn, Jung Ho ^a  

^a Seoul National University   (South Korea)

^b Sungkyunkwan University   (South Korea)

Author keywords

Asymmetric bank organizations; DRAM; High aspect ratio mats; Microarchitecture

Indexed keywords

APPLICATION PERFORMANCE; ENERGY DELAY PRODUCT; HIGH ASPECT RATIO; IN-PROCESS TECHNOLOGY; INSTRUCTIONS PER CYCLES; MEMORY ACCESS LATENCY; MICRO ARCHITECTURES; MODERN COMPUTER SYSTEMS;

ASPECT RATIO; BANDWIDTH; CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SYSTEMS; COST REDUCTION; SOCIETIES AND INSTITUTIONS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84881125193     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485955     Document Type: Conference Paper

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