3D-MAPS: 3D Massively parallel processor with stacked memory

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 188-189

  Kim, Dae Hyun ^a   Athikulwongse, Krit ^a   Healy, Michael ^a   Hossain, Mohammad ^a   Jung, Moongon ^a   Khorosh, Ilya ^a   Kumar, Gokul ^a   Lee, Young Joon ^a   Lewis, Dean ^a   Lin, Tzu Wei ^a   Liu, Chang ^a   Panth, Shreepad ^a   Pathak, Mohit ^a   Ren, Minzhen ^a   Shen, Guanhao ^a   Song, Taigon ^a   Woo, Dong Hyuk ^a   Zhao, Xin ^a   Kim, Joungho ^b   Choi, Ho ^c   Loh, Gabriel ^a   Lee, Hsien Hsin ^a   Lim, Sung Kyu ^a   more..

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c Amkor Technology Korea Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; BONDING TECHNOLOGY; DEVICE TECHNOLOGIES; GENERAL PURPOSE PROCESSORS; MASSIVELY PARALLEL PROCESSORS; MULTI-CORE PROCESSOR; POWER DENSITIES; SINGLE CYCLE; THROUGH-SILICON-VIA;

GENERAL PURPOSE COMPUTERS; OPTICAL PROJECTORS; PARALLEL PROCESSING SYSTEMS; STATIC RANDOM ACCESS STORAGE;

THREE DIMENSIONAL;

EID: 84860655377     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176969     Document Type: Conference Paper

References (5)

1. M. Koyanagi, et al. "Neuromorphic Vision Chip Fabricated Using Three-Dimensional Integration Technology", ISSCC Dig. Tech. Papers, pp. 270-271, 2001.
2. U. Kang, et al. "8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology", ISSCC Dig. Tech. Papers, pp. 130-131, 2009.
3. G. Van der Plas, et al., "Design Issues and Considerations for Low-Cost 3D TSV IC Technology", ISSCC Dig. Tech. Papers, pp. 148-149, 2010.
4. J.-S. Kim, et al. "A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4x128 I/Os Using TSV-Based Stacking", ISSCC Dig. Tech. Papers, pp. 496-498, 2011.
5. M. Healy, et al. "Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory", IEEE Custom Integrated Circuits Conf., pp. 1-4, 2010.