-
1
-
-
84890019039
-
-
[Online]. Available
-
DARPA,UHPC Program. (2010). [Online]. Available: http://www.darpa. mil
-
(2010)
DARPA,UHPC Program
-
-
-
2
-
-
79955370378
-
The future ofmicroprocessors
-
May
-
S. Borkar and A. Chien, "The future ofmicroprocessors," Commun. ACM, vol. 54, no. 5, pp. 67-77, May 2011.
-
(2011)
Commun. ACM
, vol.54
, Issue.5
, pp. 67-77
-
-
Borkar, S.1
Chien, A.2
-
3
-
-
58149229436
-
A 320 mV 56 ?W 411 GOPS/watt ultra-low voltage motion estimation accelerator in 65 nm CMOS
-
Jan.
-
H. Kaul, M. A. Anders, S.K. Mathew, S. K. Hsu, A. Agarwal, R. K. Krishnamurthy, and S. Borkar, "A 320 mV 56 ?W 411 GOPS/watt ultra-low voltage motion estimation accelerator in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 107-114, Jan. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.1
, pp. 107-114
-
-
Kaul, H.1
Anders, M.A.2
Mathew, S.K.3
Hsu, S.K.4
Agarwal, A.5
Krishnamurthy, R.K.6
Borkar, S.7
-
4
-
-
84863539197
-
Near-threshold voltage (NTV) design-Opportunities and challenges
-
H.Kaul, M. Anders, S.Hsu,A.Agarwal, R. Krishnamurthy, and S. Borkar, "Near-threshold voltage (NTV) design-Opportunities and challenges," in Proc. 49th Des. Automat. Conf., 2012, pp. 1149-1154.
-
(2012)
Proc. 49th Des. Automat. Conf.
, pp. 1149-1154
-
-
Kaul, H.1
Anders, M.2
Hsu, S.3
Agarwal, A.4
Krishnamurthy, R.5
Borkar, S.6
-
5
-
-
84860669777
-
A 280mV-to-1.2 v wideoperating-range IA-32 processor in 32 nm CMOS
-
Dig. Tech. Papers
-
S. Jain, S. Khare, S. Yada, V. Ambili, P. Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan, A. Kumar, S. K. Gb, R. Ramanarayanan, V. Erraguntla, J. Howard, S. Vangal, S. Dighe, G. Ruhl, P. Aseron, H. Wilson, N. Borkar, V. De, and S. Borkar, "A 280mV-to-1.2 V wideoperating-range IA-32 processor in 32 nm CMOS," in Proc. IEEE International Solid-State Circuits Conf. Dig. Tech. Papers, 2012, pp. 66-68.
-
(2012)
Proc. IEEE International Solid-State Circuits Conf
, pp. 66-68
-
-
Jain, S.1
Khare, S.2
Yada, S.3
Ambili, V.4
Salihundam, P.5
Ramani, S.6
Muthukumar, S.7
Srinivasan, M.8
Kumar, A.9
Gb, S.K.10
Ramanarayanan, R.11
Erraguntla, V.12
Howard, J.13
Vangal, S.14
Dighe, S.15
Ruhl, G.16
Aseron, P.17
Wilson, H.18
Borkar, N.19
De, V.20
Borkar, S.21
more..
-
6
-
-
85008053864
-
An 80-Tile sub-100-W teraflops processor in 65-nm CMOS
-
Jan.
-
S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain,V. Erraguntla, C. Roberts,Y. Hoskote, N. Borkar, and S. Borkar, "An 80-Tile sub-100-W teraflops processor in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 29-41, Jan. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.1
, pp. 29-41
-
-
Vangal, S.R.1
Howard, J.2
Ruhl, G.3
Dighe, S.4
Wilson, H.5
Tschanz, J.6
Finan, D.7
Singh, A.8
Jacob, T.9
Jain, S.10
Erraguntla, V.11
Roberts, C.12
Hoskote, Y.13
Borkar, N.14
Borkar, S.15
-
7
-
-
41549163921
-
A scalable 5-15 Gbps, 14-75 mW low-power I/O transceiver in 65 nm CMOS
-
Apr.
-
G. Balamurugan, J. Kennedy, G. Banerjee, J. Jaussi, M. Mansuri, F. O'Mahony, B. Casper, and R. Mooney, "A scalable 5-15 Gbps, 14-75 mW low-power I/O transceiver in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1010-1019, Apr. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.4
, pp. 1010-1019
-
-
Balamurugan, G.1
Kennedy, J.2
Banerjee, G.3
Jaussi, J.4
Mansuri, M.5
O'Mahony, F.6
Casper, B.7
Mooney, R.8
-
8
-
-
77952157953
-
A 47×10 Gb/s 1.4 mW/(Gb/s) Parallel Interface in 45 nm CMOS
-
Dig. Tech. Papers
-
F. O'Mahony, J. Kennedy, J. E. Jaussi, G. Balamurugan, M. Mansuri, C. Roberts, S. Shekhar, and R. Mooney, "A 47×10 Gb/s 1.4 mW/(Gb/s) Parallel Interface in 45 nm CMOS," in Proc. IEEE International Solid-State Circuits Conf. Dig. Tech. Papers, 2010, pp. 156-157.
-
(2010)
Proc. IEEE International Solid-State Circuits Conf
, pp. 156-157
-
-
O'Mahony, F.1
Kennedy, J.2
Jaussi, J.E.3
Balamurugan, G.4
Mansuri, M.5
Roberts, C.6
Shekhar, S.7
Mooney, R.8
-
9
-
-
84876772456
-
Silicon photonic microring links for high-bandwidth-density, low-power chip I/O
-
Jan.
-
N. Ophir, C. Mineo, D. Mountain, and K. Bergman, "Silicon photonic microring links for high-bandwidth-density, low-power chip I/O," IEEE Micro, vol. 33, no. 1, pp. 54-67, Jan. 2013.
-
(2013)
IEEE Micro
, vol.33
, Issue.1
, pp. 54-67
-
-
Ophir, N.1
Mineo, C.2
Mountain, D.3
Bergman, K.4
|