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Volumn , Issue , 2001, Pages 642-649

A decade of reconfigurable computing: A visionary retrospective

Author keywords

[No Author keywords available]

Indexed keywords

COARSE GRAIN RECONFIGURABLE HARDWARE; COMPUTING SCIENCE; PAPER SURVEYS; RECONFIGURABLE COMPUTING; SOFT MACHINE;

EID: 84893641728     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915091     Document Type: Conference Paper
Times cited : (477)

References (83)
  • 1
    • 84893777809 scopus 로고    scopus 로고
    • The Roadmap to Reconfigurable computing
    • Aug. 27-30, LNCS, Springer-Verlag 2000
    • R. Hartenstein, H. Grünbacher (Editors): The Roadmap to Reconfigurable computing - Proc. FPL2000, Aug. 27-30, 2000; LNCS, Springer-Verlag 2000
    • (2000) Proc. FPL2000
    • Hartenstein, R.1    Grünbacher, H.2
  • 3
    • 0141942869 scopus 로고    scopus 로고
    • The microprocessor is no more general purpose (invited paper)
    • Austin, Texas, USA, Oct. 8-10
    • R. Hartenstein: The Microprocessor is no more General Purpose (invited paper), Proc. ISIS'97, Austin, Texas, USA, Oct. 8-10, 1997.
    • (1997) Proc. ISIS'97
    • Hartenstein, R.1
  • 4
    • 0141908445 scopus 로고
    • A datapath oriented architecture for FPGAs
    • Monterey, CA, USA, February
    • D. Cherepacha and D. Lewis: A Datapath Oriented Architecture for FPGAs; Proc. FPGA'94, Monterey, CA, USA, February 1994.
    • (1994) Proc. FPGA'94
    • Cherepacha, D.1    Lewis, D.2
  • 7
    • 77956422172 scopus 로고
    • MoM - Apartly custom-design architecture compared to standard hardware
    • R. Hartenstein, A. Hirschbiel, M. Weber: MoM - apartly custom-design architecture compared to standard hardware; IEEE CompEuro 1989
    • (1989) IEEE CompEuro
    • Hartenstein, R.1    Hirschbiel, A.2    Weber, M.3
  • 8
    • 84884698360 scopus 로고
    • A novel paradigm of parallel computation and its use to implement simple high performance hardware
    • Tokyo, Japan
    • R. Hartenstein et al.: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan'90, 30th Anniversary o' Computer Society of Japan, Tokyo, Japan, 1990.
    • (1990) InfoJapan'90, 30th Anniversary O' Computer Society of Japan
    • Hartenstein, R.1
  • 9
    • 0026189343 scopus 로고
    • A novel ASIC design approach based on a new machine paradigm
    • July
    • R. Hartenstein et. al.: A Novel ASIC Design Approach Based on a New Machine Paradigm; IEEE J. SSC, Volume 26, No. 7, July 1991.
    • (1991) IEEE J. SSC , vol.26 , Issue.7
    • Hartenstein, R.1
  • 12
    • 0030364377 scopus 로고    scopus 로고
    • Colt: An experiment in wormhole run-time reconfiguration
    • Boston, MA, USA, Nov
    • R. A. Bittner et al.: Colt: An Experiment in Wormhole Run-time Reconfiguration; SPIE Photonics East'96, Boston, MA, USA, Nov. 1996.
    • (1996) SPIE Photonics East'96
    • Bittner, R.A.1
  • 13
    • 84893705878 scopus 로고    scopus 로고
    • A second opinion on dataflow machines
    • Feb. '82
    • D. Gajski et al.: A second opinion on dataflow machines; Computer, Feb. '82
    • Computer
    • Gajski, D.1
  • 15
    • 0030394522 scopus 로고    scopus 로고
    • MATRIX: A reconfigurable computing architecture with configurable instruction distribution and deployable resources
    • Napa, CA, USA, April 17-19
    • E. Mirsky, A. DeHon: MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources; Proc. IEEE FCCM'96, Napa, CA, USA, April 17-19, 1996.
    • (1996) Proc. IEEE FCCM'96
    • Mirsky, E.1    De Hon, A.2
  • 16
    • 0031360911 scopus 로고    scopus 로고
    • Garp: A MIPS processor with a reconfigurable coprocessor
    • Napa, April 16-18
    • J. Hauser and J. Wawrzynek: Garp: A MIPS Processor with a Reconfigurable Coprocessor; Proc. IEEE FCCM'97, Napa, April 16-18, 1997.
    • (1997) Proc. IEEE FCCM'97
    • Hauser, J.1    Wawrzynek, J.2
  • 17
    • 0031236158 scopus 로고    scopus 로고
    • Baring it all to Software: RAW Machines
    • September
    • E. Waingold et al.: Baring it all to Software: RAW Machines; IEEE Computer, September 1997, pp. 86-93.
    • (1997) IEEE Computer , pp. 86-93
    • Waingold, E.1
  • 18
    • 0012886693 scopus 로고    scopus 로고
    • REM ARC: Reconfigurable multimedia array coprocessor
    • Monterey, Feb
    • T. Miyamori and K. Olukotun: REM ARC: Reconfigurable Multimedia Array Coprocessor; Proc. ACM/SIGDA FPGA'98, Monterey, Feb. 1998.
    • (1998) Proc. ACM/SIGDA FPGA'98
    • Miyamori, T.1    Olukotun, K.2
  • 20
    • 0032672691 scopus 로고    scopus 로고
    • A reconfigurable arithmetic array for multimedia applications
    • Monterey, Feb. 21-23
    • A. Marshall et al.:. A Reconfigurable Arithmetic Array for Multimedia Applications; Proc. ACM/SIGDA FPGA'99, Monterey, Feb. 21-23, 1999
    • (1999) Proc. ACM/SIGDA FPGA'99
    • Marshall, A.1
  • 21
    • 0141908453 scopus 로고    scopus 로고
    • Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems
    • Napa, CA, USA, April 17-19
    • J. Becker et al.: Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems; Proc. FCCM'00, Napa, CA, USA, April 17-19, 2000.
    • (2000) Proc. FCCM'00
    • Becker, J.1
  • 22
    • 84893665784 scopus 로고    scopus 로고
    • http://www.chameleonsystems.com
  • 24
    • 84893691440 scopus 로고    scopus 로고
    • http://www.malleable.com
  • 25
    • 84893662998 scopus 로고    scopus 로고
    • http://www.broadcom.com/siliconspice.html
  • 26
    • 84893637287 scopus 로고    scopus 로고
    • http://www.sidsa.com
  • 29
    • 0002435676 scopus 로고    scopus 로고
    • PipeRench: A coprocessor for streaming multimedia acceleration
    • Atlanta, May 2-4
    • S. C. Goldstein et al.: PipeRench: A Coprocessor for Streaming Multimedia Acceleration; Proc. ISCA'99, Atlanta, May 2-4, 1999
    • (1999) Proc. ISCA'99
    • Goldstein, S.C.1
  • 30
    • 33645163663 scopus 로고
    • PADDI: Programmable arithmetic devices for digital signal processing
    • IEEE Press
    • D. Chen and J. Rabaey: PADDI: Programmable arithmetic devices for digital signal processing; VLSI Signal Processing IV, IEEE Press 1990.
    • (1990) VLSI Signal Processing IV
    • Chen, D.1    Rabaey, J.2
  • 31
    • 0026964221 scopus 로고
    • A reconfigurable multiprocessor ic for rapid prototyping of algorithmic-specific high-speed DSP data paths
    • Dec.
    • D. C. Chen, J. M. Rabaey: A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths; IEEE J. Solid-State Circuits, Vol. 27, No. 12, Dec. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , Issue.12
    • Chen, D.C.1    Rabaey, J.M.2
  • 32
    • 84884750658 scopus 로고
    • A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms
    • Kauai, Hawaii, Jan
    • A. K. W. Yeung, J.M. Rabaey: A Reconfigurable Data-driven Multiprocessor Architecture for Rapid Prototyping of High Throughput DSP Algorithms; Proc. HICSS-26, Kauai, Hawaii, Jan. 1993.
    • (1993) Proc. HICSS-26
    • Yeung, A.K.W.1    Rabaey, J.M.2
  • 33
    • 0030714347 scopus 로고    scopus 로고
    • Reconfigurable computing: The solution to low power programmable DSP
    • Germany, April
    • J. Rabaey: Reconfigurable Computing: The Solution to Low Power Programmable DSP; Proc. ICASSP'97 Munich, Germany, April 1997.
    • (1997) Proc. ICASSP'97 Munich
    • Rabaey, J.1
  • 36
    • 0029534183 scopus 로고
    • Placement and routing tools for the tryptich FPGA
    • December
    • C. Ebeling et al.: Placement and Routing Tools for the Tryptich FPGA; IEEE Trans VLSI Systems 3, No. 4, December 1995.
    • (1995) IEEE Trans VLSI Systems 3 , Issue.4
    • Ebeling, C.1
  • 42
    • 0033716233 scopus 로고    scopus 로고
    • Using general-purpose programming languages for FPGA design
    • Los Angeles, June
    • B. Hutchings, B. Nelson: Using General-Purpose Programming Languages for FPGA Design; Proc. DAC 2000, Los Angeles, June 2000
    • (2000) Proc. DAC 2000
    • Hutchings, B.1    Nelson, B.2
  • 43
    • 0030380793 scopus 로고    scopus 로고
    • Maximizing multiprocessor performance with the SUIF compiler
    • Dec.
    • M. W. Hall et al.: Maximizing Multiprocessor Performance with the SUIF Compiler; IEEE Computer, Dec. 1996
    • (1996) IEEE Computer
    • Hall, M.W.1
  • 45
    • 84893653148 scopus 로고    scopus 로고
    • Tallinn, Estonia, Aug. 31- Sept. 3, LNCS, Springer Verlag, 1998
    • R. Hartenstein, A. Keevallik (Editors): Proc. FPL'98, Tallinn, Estonia, Aug. 31- Sept. 3, 1998, LNCS, Springer Verlag, 1998
    • (1998) Proc. FPL'98
    • Hartenstein, R.1    Keevallik, A.2
  • 47
    • 0006996773 scopus 로고    scopus 로고
    • Maps: A compiler-managed memory system for RAW machines
    • Atlanta, USA, June
    • R. Barua et al.: Maps: A Compiler-Managed Memory System for RAW Machines; Proc. ISCA'99, Atlanta, USA, June, 1999.
    • (1999) Proc. ISCA'99
    • Barua, R.1
  • 48
    • 0343077459 scopus 로고    scopus 로고
    • Space-time scheduling of instruction-level parallelism on a RAW machine
    • San Jose, Oct. 4-7
    • W. Lee et al.: Space-Time Scheduling of Instruction-Level Parallelism on a RAW Machine; Proc. ASPLOS'98, San Jose, Oct. 4-7, 1998.
    • (1998) Proc. ASPLOS'98
    • Lee, W.1
  • 51
    • 77956430947 scopus 로고    scopus 로고
    • Fast compilation for pipelined reconfigurable fabrics
    • Monterey, Feb
    • M. Budiu and S. C. Goldstein: Fast Compilation for Pipelined Reconfigurable Fabrics; Proc. FPGA'99, Monterey, Feb. 1999, pp. 135-143.
    • (1999) Proc. FPGA'99 , pp. 135-143
    • Budiu, M.1    Goldstein, S.C.2
  • 52
    • 84893669041 scopus 로고
    • An integrated system for rapid prototyping of high performance data paths
    • Los Alamitos, Aug. 4-7
    • D. Chen et al.: An Integrated System for Rapid Prototyping of High Performance Data Paths; Proc. ASAP'92, Los Alamitos, Aug. 4-7, 1992
    • (1992) Proc. ASAP'92
    • Chen, D.1
  • 53
    • 0022201679 scopus 로고
    • A high-level language and silicon compiler for digital signal processing
    • Portland, May 20-23
    • P. H. Hilfinger: A High-Level Language and Silicon Compiler for Digital Signal Processing; Proc. 1985 IEEE CICC, Portland, May 20-23, 1985.
    • (1985) Proc. 1985 IEEE CICC
    • Hilfinger, P.H.1
  • 54
    • 0024913877 scopus 로고
    • A scheduling and resource allocation algorithm for hierarchical signal flow graphs
    • June
    • M. Potkonjak, J. Rabaey: A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs; Proc. DAC'89, Las Vegas, June 1989
    • (1989) Proc. DAC'89, las Vegas
    • Potkonjak, M.1    Rabaey, J.2
  • 55
    • 84893670036 scopus 로고    scopus 로고
    • A HW/SW partitioning algorithm for dynamically reconfigurable architectures
    • J. Noguera, R. Badia: A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures; Proc. DATE 2001
    • (2001) Proc. DATE
    • Noguera, J.1    Badia, R.2
  • 56
    • 84949994121 scopus 로고    scopus 로고
    • Run-time HW/SW codesign for discrete event systems using dynamically reconfigurable architectures
    • Madrid, Spain, Sept. 20-22
    • J. Noguera, R. Badia: Run-time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures; Proc. ISSS 2000 (Int'l Symp. System Synthesis), Madrid, Spain, Sept. 20-22, 2000
    • (2000) Proc. ISSS 2000 (Int'l Symp. System Synthesis)
    • Noguera, J.1    Badia, R.2
  • 57
    • 0029488826 scopus 로고
    • Technology and business: Forces driving microprocessor evolution
    • Dec
    • N. Tredennick: Technology and Business: Forces Driving Microprocessor Evolution; Proc. IEEE 83, 12 (Dec. 1995)
    • (1995) Proc. IEEE , vol.83 , pp. 12
    • Tredennick, N.1
  • 59
    • 0033488527 scopus 로고    scopus 로고
    • Pipeline vectorization for reconfigurable systems
    • April
    • M. Weinhardt, W. Luk: Pipeline Vectorization for Reconfigurable Systems; Proc. IEEE FCCM, April 1999
    • (1999) Proc. IEEE FCCM
    • Weinhardt, M.1    Luk, W.2
  • 60
    • 85013607448 scopus 로고    scopus 로고
    • NAPA C: Compiling for a hybrid RISC/FPGA architecture
    • April
    • M. Gokhale, J. Stone: NAPA C: Compiling for a hybrid RISC/FPGA architecture; Proc. IEEE FCCM April 1998
    • (1998) Proc. IEEE FCCM
    • Gokhale, M.1    Stone, J.2
  • 62
    • 0030416290 scopus 로고    scopus 로고
    • A general approach in system design integrating reconfigurable accelerators
    • Austin, TX, Oct. 9-11
    • J. Becker et al.: A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. IEEE ISIS'96; Austin, TX, Oct. 9-11, 1996
    • (1996) Proc. IEEE ISIS'96
    • Becker, J.1
  • 63
    • 77956446766 scopus 로고    scopus 로고
    • A novel sequencer hardware for application specific computing
    • Zurich, Switzerland, July 14-16
    • M. Herz, et al.: A Novel Sequencer Hardware for Application Specific Computing; Proc. ASAP'97, Zurich, Switzerland, July 14-16, 1997
    • (1997) Proc. ASAP'97
    • Herz, M.1
  • 66
    • 0026191311 scopus 로고
    • The ADAM design planning engine
    • July
    • D. Knapp & et al.: The ADAM Design Planning Engine, IEEE Trans CAD, July 1991
    • (1991) IEEE Trans CAD
    • Knapp, D.1
  • 67
    • 84893711700 scopus 로고
    • Design Assistance for CAD Frameworks
    • Hamburg, Germany, Sept. 7-10
    • J. Lopez et al.: Design Assistance for CAD Frameworks; Proc. EURO-DAC'62, Hamburg, Germany, Sept. 7-10, 1992
    • (1992) Proc. EURO-DAC'62
    • Lopez, J.1
  • 68
    • 0031635599 scopus 로고    scopus 로고
    • A methodology for guided behavioural level optimization
    • San Francisco, June 15-19
    • L. Guerra et al.: A Methodology for Guided Behavioural Level Optimization; Proc. DAC'98, San Francisco, June 15-19, 1998
    • (1998) Proc. DAC'98
    • Guerra, L.1
  • 69
    • 16244380727 scopus 로고    scopus 로고
    • Global multimedia design exploration using accurate memory organization feedback
    • A. Vandecapelle et al.: Global Multimedia Design Exploration using Accurate Memory organization Feedback; Proc. DAC 1999
    • (1999) Proc. DAC
    • Vandecapelle, A.1
  • 70
    • 84893700329 scopus 로고    scopus 로고
    • Dynamic algorithms for minimizing memory bandwidth in high throughput telecom and multimedia
    • TS1, Editions Hermès
    • T. Omnès et al: Dynamic Algorithms for Minimizing Memory Bandwidth in High throughput Telecom and Multimedia; in: Techniques de Parallelization Automatique, TS1, Editions Hermès, 1999
    • (1999) Techniques de Parallelization Automatique
    • Omnès, T.1
  • 71
    • 0033279857 scopus 로고    scopus 로고
    • Minimizing the required memory bandwidth in VLSI system realizations
    • Dec.
    • S. Wuytack et al: Minimizing the required Memory Bandwidth in VLSI System Realizations; IEEE Trans. VLSI Systems, Dec. 1999
    • (1999) IEEE Trans. VLSI Systems
    • Wuytack, S.1
  • 72
    • 84893711431 scopus 로고    scopus 로고
    • Algorithms for high-level synthesis
    • Dec'89
    • P. Paulin et al.: Algorithms for High-Level Synthesis; IEEE Design & Test, Dec'89
    • IEEE Design & Test
    • Paulin, P.1
  • 73
    • 0033698643 scopus 로고    scopus 로고
    • Interactive co-design of high throughput embedded multimedia
    • F. Cathoor et al: Interactive Co-design of High Throughput Embedded Multimedia; DAC 2000
    • (2000) DAC
    • Cathoor, F.1
  • 74
    • 0029181969 scopus 로고
    • Optimization of memory organization and partitioning for decreased size and power in video and image processing systems
    • Aug.
    • L. Nachtergaele et al.: Optimization of Memory Organization and Partitioning for Decreased Size and Power in Video and Image Processing Systems; Proc. IEEE Workshop on Memory Technology, Aug. 1995
    • (1995) Proc. IEEE Workshop on Memory Technology
    • Nachtergaele, L.1
  • 76
    • 0030110560 scopus 로고    scopus 로고
    • PSM: An object-oriented synthesis approach to multiprocessor design
    • March
    • P.-A. Hsiung et al.: PSM: An Object-oriented Synthesis Approach to Multiprocessor Design; IEEE Trans VLSI Systems 4/1, March 1999
    • (1999) IEEE Trans VLSI Systems , vol.4 , Issue.1
    • Hsiung, P.-A.1
  • 77
    • 0004591770 scopus 로고    scopus 로고
    • Power efficient media processor design space exploration
    • New Orleans, June 21-25
    • J. Kin et al.: Power Efficient Media Processor Design Space Exploration; Proc. DAC'99, New Orleans, June 21-25, 1999
    • (1999) Proc. DAC'99
    • Kin, J.1
  • 81
    • 84893652433 scopus 로고    scopus 로고
    • Göttingen, Germany Sept. 13-15, LNCS, Springer Verlag, 2000
    • D. Soudris, P. Pirsch, E. Barke (Editors): Proc. PATMOS 2000; Göttingen, Germany Sept. 13-15, 2000; LNCS, Springer Verlag, 2000
    • (2000) Proc. PATMOS 2000
    • Soudris, D.1    Pirsch, P.2    Barke, E.3
  • 82
    • 84893672500 scopus 로고    scopus 로고
    • Lower bounds on the power consumption in scheduled data flow graphs with resource constraints
    • Mrch
    • L. Kruse et al.: Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints; Proc. DATE, Mrch 2000.
    • (2000) Proc. DATE
    • Kruse, L.1
  • 83
    • 84893684985 scopus 로고    scopus 로고
    • High-Performance Computing: über Szenen und Krisen
    • Dagstuhl, June
    • R. Hartenstein (invited paper): High-Performance Computing: über Szenen und Krisen; GI/ITG Workshop on Custom Computing, Dagstuhl, June 1996
    • (1996) GI/ITG Workshop on Custom Computing
    • Hartenstein, R.1


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