A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems

Microprocessors and Microsystems

Volumn 38, Issue 6, 2014, Pages 567-580

  Miele, Antonio ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

Dependability analysis; Fault injection; Multiprocessors; SystemC; Transaction level modeling

Indexed keywords

ARCHITECTURE; EMBEDDED SYSTEMS; MULTIPROCESSING SYSTEMS;

DEPENDABILITY ANALYSIS; FAULT INJECTION; MULTIPROCESSORS; SYSTEMC; TRANSACTION LEVEL MODELING;

DATA FLOW ANALYSIS;

EID: 84906326908     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2014.05.008     Document Type: Article

References (42)

1. C. Constantinescu Trends and challenges in VLSI circuit reliability IEEE Micro 4 2003 14 19
2. A. Benso, and P. Prinetto Fault Injection Techniques and Tools for Embedded Systems 2003 Kluwer Academic Publishers
3. D. Lee, and J. Na A novel simulation fault injection method for dependability analysis IEEE Des. Test Comput. 26 2009 50 61
4. A. Pellegrini, K. Constantinides, D. Zhang, S. Sudhakar, V. Bertacco, and T. Austin CrashTest: a fast high-fidelity FPGA-based resiliency analysis framework Intl. Conf. on Computer Design 2008 IEEE 363 370
5. M. Aguirre, J. Tombs, F. Muoz, V. Baena, H. Guzman, J. Napoles, A. Torralba, A. Fernandez-Leon, F. Tortosa-Lopez, and D. Merodio Selective protection analysis using a SEU emulator: testing protocol and case study over the LEON2 processor IEEE Trans. Nucl. Sci. 54 2007 951 956
6. P. Civera, L. Macchiarulo, M. Rebaudengo, M.S. Reorda, and M. Violante An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits J. Electron. Test. 18 2002 261 271
7. E. Touloupis, J. Flint, V. Chouliaras, and D. Ward Study of the effects of SEU-induced faults on a pipeline protected microprocessor IEEE Trans. Comput. 56 2007 1585 1596
8. D. de Andrés, J. Ruiz, D. Gil, and P. Gil Fault emulation for dependability evaluation of VLSI systems IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16 2008 422 431
9. G. Beltrame, L. Fossati, and D. Sciuto ReSP: a nonintrusive transaction-level reflective MPSoC simulation platform for design space exploration IEEE Trans. CAD Integr. Circ. Syst. 28 2009 1857 1869
10. SystemC, Open SystemC Initiative. < www.systemc.org > (accessed 10.10.13).
11. C. Bolchini, A. Miele, and D. Sciuto Fault models and injection strategies in SystemC specifications Proc. Euromicro Conf. on Digital System Design 2008 IEEE 88 95
12. A. Manuzzato, P. Rech, S. Gerardin, A. Paccagnella, L. Sterpone, and M. Violante Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs Intl. Symp. on Defect and Fault-Tolerance in VLSI Systems 2007 IEEE 79 86
13. D. Appello, P. Bernardi, S. Gerardin, M. Grosso, A. Paccagnella, P. Rech, and M.S. Reorda DfT reuse for low-cost radiation testing of SoCs: a case study Proc. VLSI Test Symposium 2009 IEEE 276 281
14. J. Carreira, H. Madeira, and J. Silva Xception: a technique for the experimental evaluation of dependability in modern computers IEEE Trans. Softw. Eng. 24 1998 125 136
15. M. Portela-García, C. López-Ongil, M. García- Valderas, and L. Entrena Fault injection in modern microprocessors using on-chip debugging infrastructures IEEE Trans. Dependable Secure Comput. 8 2011 308 314
16. L. Entrena, M. Garcia-Valderas, R. Fernandez-Cardenal, A. Lindoso, M. Portela, and C. Lopez-Ongil Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection IEEE Trans. Comput. 61 2012 313 322
17. A. da Silva, and S. Sanchez LEON3 ViP: a virtual platform with fault injection capabilities Proc. Conf. on Digital System Design (DSD) 2010 IEEE 813 816
18. R. Shafik, P. Rosinger, and B. Al-Hashimi SystemC-based minimum intrusive fault injection technique with improved fault representation Proc. Intl. On-Line Testing Symposium 2008 IEEE 99 104
19. J. Perez, M. Azkarate-askasua, and A. Perez Codesign and simulated fault injection of safety-critical embedded systems using SystemC European Dependable Computing Conference 2010 IEEE 221 229
20. A. Bosio, G.D. Natale, LIFTING: a flexible open-source fault simulator, in: Proc. Asian Test Symposium, pp. 35-40.
21. F. Lu, G.D. Natale, M.-L. Flottes, B. Rouzeyre, Laser-induced fault simulation, in: Proc. Conf. Digital System Design, pp. 609-614.
22. A. Ejlali, and S. Miremadi Error propagation analysis using FPGA-based SEU-fault injection Microelectron. Reliab. 48 2008 319 328
23. R. Mariani, and G. Boschi A systematic approach for failure modes and effects analysis of system-on-chips Intl. On-Line Testing Symposium 2007 IEEE 187 188
24. Y.-Y. Chen, C.-H. Hsu, and K.-L. Leu SoC-level risk assessment using FMEA approach in system design with SystemC Proc. Intl. Symp. Industrial Embedded Systems (SIES) 2009 IEEE 82 89
25. A. Rohani, and H.-R. Zarandi An analysis of fault effects and propagations in AVR microcontroller ATmega103(L) Proc. Int. Conf. on Availability, Reliability and Security (ARES) 2009 IEEE 166 172
26. A. Ammari, K. Hadjiat, and R. Leveugle Combined fault classification and error propagation analysis to refine RT-level dependability evaluation J. Electron. Test. 21 2005 365 376
27. S. Mukherjee, C. Weaver, J. Emer, S. Reinhardt, and T. Austin A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor Intl. Symp. on Microarchitecture 2003 ACM 29 40
28. V. Sridharan, and D. Kaeli Eliminating microarchitectural dependency from architectural vulnerability Proc. Int. Symp. on High Performance Computer Architecture (HPCA) 2009 IEEE 117 128
29. I. Oz, H. Topcuoglu, M. Kandemir, and O. Tosun Quantifying thread vulnerability for multicore architectures Proc. of Euromicro Intl. Conf. on Parallel, Distributed and Network-Based Processing (PDP) 2011 IEEE 32 39
30. R. Baranowski, S. Di Carlo, N. Hatami, M.E. Imhof, M.A. Kochte, P. Prinetto, H.-J. Wunderlich, and C.G. Zoellin Efficient multi-level fault simulation of HW/SW systems for structural faults Sci. China Inform. Sci. 54 2011 1784 1796
31. G. Beltrame, C. Bolchini, and A. Miele Multi-level fault modeling for transaction-level specifications Proc. of the Great Lakes Symposium on VLSI (GLSVLSI) 2009 ACM 87 92
32. S. Reiter, M. Pressler, A. Viehl, O. Bringmann, and W. Rosenstiel Reliability assessment of safety-relevant automotive systems in a model-based design flow Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 2013 ACM 417 422
33. M. Michael, D. Grobe, R. Drechsler, Analyzing dependability measures at the electronic system level, in: Proc. Forum on Specification and Design Languages (FDL), pp. 1-8.
34. C. Bolchini, and A. Miele An application-level dependability analysis framework for embedded systems Proc. Int. Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2011 IEEE 171 178
35. Politecnico di Milano, ReSP web site. < http://code.google.com/p/resp- sim/ > (accessed 10.10.13).
36. A. Miele, C. Pilato, and D. Sciuto A simulation-based framework for the exploration of mapping solutions on heterogeneous MPSoCs Int. J. Embed. Real-Time Commun. Syst. (IJERTCS) 4 2013 22 41
37. ARM, Application Binary Interface (ABI) for the ARM Architecture. < http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.swdev.abi/ index.html > (accessed 10.10.13).
38. S. Campagna, and M. Violante An hybrid architecture to detect transient faults in microprocessors: an experimental validation Design, Automation Test in Europe Conf. (DATE) 2012 IEEE 1433 1438
39. A. Benso, M. Rebaudengo, L. Impagliazzo, and P. Marmo Fault-list collapsing for fault-injection experiments Proc. Annual Reliability and Maintainability Symposium 1998 IEEE 383 388
40. S. Hari, S. Adve, H. Naeimi, and P. Ramachandran Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults Proc. Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2012 ACM 123 134
41. R. Leveugle, A. Calvez, P. Maistri, and P. Vanhauwaert Statistical fault injection: quantified error and confidence Proc. Conf. Design, Automation, and Test in Europe 2009 IEEE 502 506
42. O. Goloubeva, M. Rebaudengo, M.S. Reorda, and M. Violante Soft-error detection using control flow assertions Proc. Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT) 2003 IEEE 581 588