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Volumn , Issue , 2012, Pages 123-134

Relyzer: Exploiting application-level fault equivalence to analyze application resiliency to transient faults

Author keywords

architecture; hardware reliability evaluation; low cost hardware resiliency; silent data corruption; transient faults

Indexed keywords

BENCHMARK SUITES; DATA CORRUPTION; FAULT EQUIVALENCE; FAULT INJECTION; FAULT SITES; HARDWARE FAULTS; HARDWARE RELIABILITY EVALUATION; LOW-COST HARDWARE RESILIENCY; LOW-COST SOLUTION; ORDERS OF MAGNITUDE; PRUNING TECHNIQUES; RELIABLE OPERATION; TRANSIENT FAULTS;

EID: 84858759524     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2150976.2150990     Document Type: Conference Paper
Times cited : (139)

References (27)
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    • Z. Kalbarczyk, R. Iyer, G. Ries, J. Patel, M. Lee, and Y. Xiao. Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation. Software Engineering, IEEE Transactions on, 25(5):619 -632, sep/oct 1999.
    • (1999) Software Engineering, IEEE Transactions on , vol.25 , Issue.5 , pp. 619-632
    • Kalbarczyk, Z.1    Iyer, R.2    Ries, G.3    Patel, J.4    Lee, M.5    Xiao, Y.6
  • 15
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    • Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset
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    • Martin, M.1
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    • Hierarchical Fault Simulation using Behavioral and Gate Level Hardware Models
    • Nov.
    • S. Mirkhani, M. Lavasani, and Z. Navabi. Hierarchical Fault Simulation using Behavioral and Gate Level Hardware Models. In Asian Test Symposium (ATS), pages 374-379, Nov. 2002.
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    • Mirkhani, S.1    Lavasani, M.2    Navabi, Z.3
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    • Virtutech. Website
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.