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Volumn , Issue , 2011, Pages 32-39

Quantifying thread vulnerability for multicore architectures

Author keywords

Fault tolerance; multithreading; Reliability

Indexed keywords

APPLICATION DOMAINS; ARCHITECTURAL COMPONENTS; EXECUTION CYCLES; EXPERIMENTAL EVALUATION; LOW-POWER OPERATING MODES; MODERN ARCHITECTURES; MULTI-CORE MACHINES; MULTI-CORES; MULTI-THREADED APPLICATION; MULTICORE ARCHITECTURES; MULTITHREADING; REGISTER FILES; SOURCE CODES; TRANSIENT ERRORS; TRANSISTOR SIZE;

EID: 79954985942     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2011.75     Document Type: Conference Paper
Times cited : (3)

References (10)
  • 7
    • 63549095070 scopus 로고    scopus 로고
    • The parsec benchmark suite: Characterization and architectural implications
    • C. Bienia, S. Kumar, J. P. Singh, and K. Li, "The parsec benchmark suite: Characterization and architectural implications," in Proc. PACT, 2008.
    • (2008) Proc. PACT
    • Bienia, C.1    Kumar, S.2    Singh, J.P.3    Li, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.