Selective protection analysis using a SEU emulator: Testing protocol and case study over the Leon2 processor

IEEE Transactions on Nuclear Science

Volumn 54, Issue 4, 2007, Pages 951-956

  Aguirre, M A ^a,b   Tombs, J N ^a,b   Munoz F ^b   Baena, V ^b   Guzman H ^b   Napoles J ^b   Torralba, A ^a,b   Fernandez Leon A ^c   Tortosa Lopez F ^c   Merodio, D ^c  

^a IEEE

^b UNIVERSIDAD DE SEVILLA   (Spain)

^c EUROPEAN SPACE AGENCY   (Netherlands)

Author keywords

ASIC; Fault injection; FPGA reconfiguration; FPGA based emulation; Multi bit upset; Single event upset (SEU)

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM PROCESSORS; REDUNDANCY; SILICON; SPACE APPLICATIONS;

FAULT INJECTION; LEON2 PROCESSOR; PRODUCTION COSTS; SEU EMULATOR; SUBCIRCUITS;

VLSI CIRCUITS;

EID: 34548108316     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.895550     Document Type: Conference Paper

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