-
1
-
-
0029732375
-
IBM Experiments in Soft Fails in Computer Electronics (1978-1994)
-
Jan
-
J.F. Ziegler et al., "IBM Experiments in Soft Fails in Computer Electronics (1978-1994)", IBM J. Research and Development, vol. 40, no. 1, pp. 3-18, Jan. 1996
-
(1996)
IBM J. Research and Development
, vol.40
, Issue.1
, pp. 3-18
-
-
Ziegler, J.F.1
-
2
-
-
0036923569
-
Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies
-
P. E. Dodd, et al., "Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies," in Proc. Int. Electron Device Meeting, 2002, pp. 333-336
-
(2002)
Proc. Int. Electron Device Meeting
, pp. 333-336
-
-
Dodd, P.E.1
-
3
-
-
70350353240
-
-
G. Gasiot et al., Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65nm CMOS Technology, NSREC 2006
-
G. Gasiot et al., "Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65nm CMOS Technology", NSREC 2006
-
-
-
-
4
-
-
28444479961
-
-
Cypress Semiconductors Corporation
-
J. F. Ziegler, H. Puchner, "SER - Histrory, Trends and Challenges, a Guide for Designing with Memory ICs", Cypress Semiconductors Corporation, 2004
-
(2004)
SER - Histrory, Trends and Challenges, a Guide for Designing with Memory ICs
-
-
Ziegler, J.F.1
Puchner, H.2
-
5
-
-
29344472607
-
Radiation-Induced Soft Errors in Advanced Semiconductor Technologies
-
Sept
-
R. Baumann, "Radiation-Induced Soft Errors in Advanced Semiconductor Technologies", IEEE TNS Device and Material Reliability, Vol. 5, Sept. 2005, pp. 305-316
-
(2005)
IEEE TNS Device and Material Reliability
, vol.5
, pp. 305-316
-
-
Baumann, R.1
-
6
-
-
11044239423
-
Production and Propagation of Single-Event Transients in High-Speed Digital Logic ICs
-
Dec
-
P. Dodd et al., "Production and Propagation of Single-Event Transients in High-Speed Digital Logic ICs", IEEE TNS Nucl. Sci. Vol. 51, Dec. 2004, pp. 3278-3284
-
(2004)
IEEE TNS Nucl. Sci
, vol.51
, pp. 3278-3284
-
-
Dodd, P.1
-
7
-
-
11044223633
-
Single Event Transient Pulsewidth Temporal Latch Technique
-
Dec
-
P. Eaton et al., "Single Event Transient Pulsewidth Temporal Latch Technique", IEEE TNS Nucl. Sci. Vol. 51, Dec. 2004, pp. 3365-3368
-
(2004)
IEEE TNS Nucl. Sci
, vol.51
, pp. 3365-3368
-
-
Eaton, P.1
-
8
-
-
52049108892
-
A Built-In Self-Test Scheme for Soft Error Rate Characterization
-
A. Sanyal et al., "A Built-In Self-Test Scheme for Soft Error Rate Characterization", IEEE International On-Line Testing Symposium 2008, pp. 65-70
-
(2008)
IEEE International On-Line Testing Symposium
, pp. 65-70
-
-
Sanyal, A.1
-
9
-
-
0028547917
-
Tutorial on semiconductor memory testing
-
Nov
-
B.F Cockburn, "Tutorial on semiconductor memory testing", Journal of Electronic Testing: Theory and Application, Vol. 5, No. 4, Nov. 1994, pp. 321-336
-
(1994)
Journal of Electronic Testing: Theory and Application
, vol.5
, Issue.4
, pp. 321-336
-
-
Cockburn, B.F.1
-
10
-
-
0033309980
-
Logic BIST for large Industrial Designs: Real Issues and Case Studies
-
G. Hetherington et al., "Logic BIST for large Industrial Designs: Real Issues and Case Studies", IEEE International Test Conference, 1999, pp. 358-367
-
(1999)
IEEE International Test Conference
, pp. 358-367
-
-
Hetherington, G.1
-
11
-
-
0032680143
-
A programmable BIST core for embedded DRAM
-
Jan-March
-
C.-T. Huang et al., "A programmable BIST core for embedded DRAM", IEEE Design & Test of Computers, Vol. 16, No. 1, Jan-March 1999, pp. 59-70
-
(1999)
IEEE Design & Test of Computers
, vol.16
, Issue.1
, pp. 59-70
-
-
Huang, C.-T.1
-
13
-
-
0027610855
-
Built-In Self Diagnosis for Repairable Embedded RAMs
-
June
-
R. Treuer, V.K. Agarwal, "Built-In Self Diagnosis for Repairable Embedded RAMs", IEEE Design and Test of Computers, Vol. 10, No. 2, June 1993, pp. 24-33
-
(1993)
IEEE Design and Test of Computers
, vol.10
, Issue.2
, pp. 24-33
-
-
Treuer, R.1
Agarwal, V.K.2
-
14
-
-
0006642848
-
Processor-Programmable Memory BIST for Bus-Connected Embedded Memories
-
C.-H. Tsai, C.-W. Wu, "Processor-Programmable Memory BIST for Bus-Connected Embedded Memories", ACM Design Automation Conference, 2001, pp. 325-330
-
(2001)
ACM Design Automation Conference
, pp. 325-330
-
-
Tsai, C.-H.1
Wu, C.-W.2
-
15
-
-
0032203003
-
Processor-based Built-In Self-Test for Embedded DRAM
-
Nov
-
J. Dreibelbis et al., "Processor-based Built-In Self-Test for Embedded DRAM", IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, Nov. 1998, pp. 1731-1740
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.33
, Issue.11
, pp. 1731-1740
-
-
Dreibelbis, J.1
-
16
-
-
0142215942
-
Exploiting programmable BIST for the diagnosis of embedded memory cores
-
D. Appello et al, "Exploiting programmable BIST for the diagnosis of embedded memory cores", IEEE Int'l Test Conference, 2003, pp. 379-385
-
(2003)
IEEE Int'l Test Conference
, pp. 379-385
-
-
Appello, D.1
-
17
-
-
84961244832
-
Macro Testability: The results of production device applications
-
F. Bouwman, et al., "Macro Testability: the results of production device applications", IEEE International Test Conference, 1992, pp. 232-241
-
(1992)
IEEE International Test Conference
, pp. 232-241
-
-
Bouwman, F.1
-
18
-
-
0034247857
-
A Fast and Low-Cost Testing Technique for Core-Base System-Chips
-
Aug
-
I. Ghosh et al., "A Fast and Low-Cost Testing Technique for Core-Base System-Chips", IEEE TNS on CAD, Vol. 19, No. 8, Aug. 2000, pp. 863-877
-
(2000)
IEEE TNS on CAD
, vol.19
, Issue.8
, pp. 863-877
-
-
Ghosh, I.1
-
19
-
-
70350399669
-
-
C. Stroud, A Designer's Guide to Built-In Self-Test, Kluwer Academic Publishers, 2002
-
C. Stroud, "A Designer's Guide to Built-In Self-Test, Kluwer Academic Publishers, 2002
-
-
-
-
20
-
-
33646923423
-
Testing logic cores using a BIST P1500 compliant approach: A case of study
-
P. Bernardi et al., "Testing logic cores using a BIST P1500 compliant approach: a case of study", IEEE Design, Automation and Test in Europe Conf., 2005, pp. 288-233
-
(2005)
IEEE Design, Automation and Test in Europe Conf
, pp. 288-233
-
-
Bernardi, P.1
-
21
-
-
17644398178
-
Software-based self-testing of embedded processors
-
April
-
N. Kranitis et al., "Software-based self-testing of embedded processors", IEEE Transactions on Computers, Vol. 54, No. 4, April 2005, pp. 461-475
-
(2005)
IEEE Transactions on Computers
, vol.54
, Issue.4
, pp. 461-475
-
-
Kranitis, N.1
-
22
-
-
0003659767
-
Standard for Embedded Core Test (SECT),
-
IEEE 1500
-
IEEE 1500 Standard for Embedded Core Test (SECT), 2005
-
(2005)
-
-
-
23
-
-
70350400889
-
Standard Test Access Port and Boundary-Scan Architecture (JTAG),
-
IEEE 1149.1
-
IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture (JTAG), 1994
-
(1994)
-
-
-
25
-
-
34547254841
-
A Comprehensive Study on the Soft-Error Rate of Flip-Flops From 90-nm Production Libraries
-
March
-
T. Heijmen at al., "A Comprehensive Study on the Soft-Error Rate of Flip-Flops From 90-nm Production Libraries", IEEE TNS Nucl. Sci. Vol. 7m March 2007, pp. 84-96
-
(2007)
IEEE TNS Nucl. Sci
, vol.7 m
, pp. 84-96
-
-
Heijmen, T.1
at al2
|