Multi-level fault modeling for transaction-level specifications

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2009, Pages 87-92

  Beltrame, Giovanni ^a   Bolchini, Cristiana ^b   Miele, Antonio ^b  

^a EUROPEAN SPACE AGENCY   (Netherlands)

^b POLITECNICO DI MILANO   (Italy)

Author keywords

Fault Modeling; Soft Error; System Level Design; TLM

Indexed keywords

ABSTRACTION LEVEL; DEPENDABILITY ANALYSIS; DESIGN PHASIS; FAULT MODELING; LEVELS OF ABSTRACTION; MULTI-LEVEL; NETWORK ON CHIP; ON-LINE TESTING; SOFT ERROR; SYSTEM-LEVEL DESIGN; TLM; TRANSACTION LEVEL; TRANSACTION LEVEL MODELS; WORK FOCUS;

ABSTRACTING; DESIGN; ELECTRIC NETWORK TOPOLOGY; ERROR CORRECTION; FAULT TOLERANT COMPUTER SYSTEMS; LAKES; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; SPECIFICATIONS; SWITCHING CIRCUITS;

FAULT TOLERANCE;

EID: 70350605293     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1531542.1531565     Document Type: Conference Paper

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