Sensitivity evaluation of TMR-hardened circuits to multiple seus induced by alpha particles in commercial SRAM-based FPGAs

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2007, Pages 79-86

  Manuzzato, A ^a   Rech, P ^a   Gerardin, S ^a   Paccagnella, A ^a   Sterpone, L ^b   Violante, M ^b  

^a UNIVERSITY OF PADOVA   (Italy)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURATION MEMORY; CONSTANT FLUXES; EXPERIMENTAL ANALYSIS; SENSITIVITY EVALUATION;

ALPHA PARTICLES; DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; HARDENING; STATIC RANDOM ACCESS STORAGE;

COMPUTER CONTROL SYSTEMS;

EID: 77649315846     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2007.57     Document Type: Conference Paper

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