Study of the effects of SEU-Induced Faults on a pipeline protected microprocessor

IEEE Transactions on Computers

Volumn 56, Issue 12, 2007, Pages 1585-1596

  Touloupis, Emmanuel ^a   Flint, James A ^b   Chouliaras, Vassilios A ^b   Ward, David D ^c  

^a InAccess Networks   (Greece)

^b LOUGHBOROUGH UNIVERSITY   (United Kingdom)

^c MIRA Limited   (United Kingdom)

Author keywords

Fault injection; Fault modeling and simulation; Fault tolerance; Microprocessor test; SEU; Soft error

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; STATISTICAL METHODS;

FAULT INJECTION; FAULT MODELING; FAULT SIMULATION; MICROPROCESSOR TEST;

FAULT TOLERANCE;

EID: 36348947597     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.70766     Document Type: Article

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