SoC-level risk assessment using FMEA approach in system design with systemC

Proceedings - 2009 IEEE International Symposium on Industrial Embedded Systems, SIES 2009

Volumn , Issue , 2009, Pages 82-89

  Chen, Yung Yuan ^a   Hsu, Chung Hsien ^a   Leu, Kuen Long ^b  

^a CHUNG HUA UNIVERSITY   (Taiwan)

^b NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTION LEVEL; CRITICAL COMPONENT; CRITICAL ISSUES; DESIGN INDUSTRY; EARLY DESIGN PHASE; FAILURE MODE AND EFFECTS ANALYSIS; RADIATION-INDUCED; RISK MODEL; SAFETY CRITICAL APPLICATIONS; SAFETY-CRITICAL; SIMULATION PERFORMANCE; SOC DESIGNS; SOFT ERROR; SYSTEM DEPENDABILITY; SYSTEM DESIGN; SYSTEM FAILURES; SYSTEM ON CHIPS; SYSTEM VERIFICATIONS; SYSTEMC; TRANSACTION LEVEL MODELING; VERY DEEP SUB MICRONS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COST REDUCTION; EMBEDDED SYSTEMS; ERROR CORRECTION; FAILURE ANALYSIS; INTELLIGENT SYSTEMS; LOGIC DESIGN; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; QUALITY ASSURANCE; RADIATION EFFECTS; RELIABILITY ANALYSIS; RISK ANALYSIS; RISK ASSESSMENT; RISK MANAGEMENT; SAFETY FACTOR; SIMULATORS; SYSTEMS ENGINEERING;

MATHEMATICAL MODELS;

EID: 70449453602     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIES.2009.5196199     Document Type: Conference Paper

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