Crash test: A fast High-Fidelity FPGA-Based resiliency analysis framework

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 363-370

  Pellegrini, Andrea ^a   Constantinides, Kypros ^a   Zhang, Dan ^a   Sudhakar, Shobana ^a   Bertacco, Valeria ^a   Austin, Todd ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS PROCESS; ANALYSIS SYSTEMS; COMPREHENSIVE DESIGNS; CRASH TESTS; DESIGN HOUSE; EXPERIMENTAL EVALUATIONS; FAILURE RATES; FAULT ANALYSIS; FAULT INJECTIONS; GATE OXIDES; HARDWARE DESCRIPTIONS; HARDWARE EMULATIONS; HIGH FIDELITIES; HIGH-FIDELITY ANALYSIS; INTEGRATED CIRCUIT COMPONENTS; INTEGRATED SYSTEMS; NETLIST; ORDERS OF MAGNITUDES; ROBUST DESIGNS; SILICON TECHNOLOGIES; SOFTWARE APPLICATIONS; SOFTWARE-BASED; SYSTEM LEVELS; SYSTEM ON CHIPS; TRANSIENT FAULTS;

BUCKLING; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; INTEGRATED OPTICS; MACHINE DESIGN; QUALITY ASSURANCE; SAFETY FACTOR;

FAILURE ANALYSIS;

EID: 62349129528     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751886     Document Type: Conference Paper

References (22)

1. Xilinx University Program: Xilinx XUP Virtex-II Pro Development System. http://www.xilinx.com/univ/xupv2p.html, 2005.
2. T. M. Austin. DIVA: A reliable substrate for deep submicron microarchitecture design. In MICRO-32, 1999.
3. J. E. Bartlett et al. Organizational research: Determining appropriate sample size in survey research. Information Technology, Learning, and Performance Journal, 19(1):43-50, 2001.
4. S. Borkar. Microarchitecture and design challenges for gigascale integration. In MICRO, Keynote Presentation, 2004.
5. S. Borkar et al. Design and reliability challenges in nanometer technologies. In DAC-41, 2004.
6. F. A. Bower et al. A mechanism for online diagnosis of hard faults in microprocessors. In MICRO, 2005.
7. M. L. Bushnell et al. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Kluwer Academic Publishers, Boston, 2000.
8. C. Chang et al. BEE2: A high-end reconfigurable computing system. IEEE Design & Test of Computers, 22(2), 2005.
9. P. Civera et al. FPGA-based fault injection techniques for fast evaluation of fault tolerance in VLSI circuits. Lecture Notes in Computer Science, 2147, 2001.
10. J. Gaisler. A portable and fault-tolerant microprocessor based on the SPARC V8 architecture. In DSN, pages 409-415, 2002.
11. R. Guo et al. Evaluation of test metrics: Stuck-at, bridge coverage estimate and gate exhaustive. In VTS, 2006.
12. G. A. Kanawati et al. FERRARI: A flexible software-based fault and error injection system. IEEE Trans. Computers, 44(2):248-260, 1995.
13. Li-Shiuan Peh. Flow Control and Micro-Architectural Mechanisms for Extending the Performance of Interconnection Networks. PhD thesis, Stanford, 2001.
14. C. López-Ongil et al. An autonomous FPGA-based emulation system for fast fault tolerant evaluation. In FPL, 2005.
15. C. McNairy and R. Bhatia. Montecito: A dual-core, dual-thread Itanium processor. IEEE Micro, 25(2):10-20, 2005.
16. Mei-Chen et al. Fault injection techniques and tools. IEEE Computer, 30(4):75-82, 1997.
17. G. P. Saggese et al. Microprocessor sensitivity to failures: Control vs execution and combinational vs sequential logic. In DSN, 2005.
18. K. Sankaralingam et al. Exploiting ILP, DLP, and TLP using polymorphism in the TRIPS architecture. In ISCA, 2003.
19. D. P. Siewiorek and R. S. Swarz. Reliable computer systems: Design and evaluation, 3rd edition. AK Peters, Ltd, 1998.
20. J. Srinivasan et al. The impact of technology scaling on lifetime reliability. In DSN-34, pages 177-186, 2004.
21. N. J. Wang et al. Characterizing the effects of transient faults on a high-performance processor pipeline. In DSN, 2004.
22. J. Wawrzynek et al. RAMP: A research accelerator for multiple processors. Technical report, Berkeley, 2006.