An hybrid architecture to detect transient faults in microprocessors: An experimental validation

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 1433-1438

  Campagna, Salvatore ^a   Violante, Massimo ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

tbd

Indexed keywords

COST EFFECTIVENESS; FAULT TOLERANCE; IONIZING RADIATION; REDUNDANCY;

APPLICATION FIELDS; COMMERCIAL OFF-THE-SHELF COMPONENTS; EXPERIMENTAL EVALUATION; EXPERIMENTAL VALIDATIONS; FAULT-TOLERANT ARCHITECTURES; HYBRID ARCHITECTURES; PERFORMANCE ISSUES; RISC MICROPROCESSORS;

FAULT DETECTION;

EID: 84862076035     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176590     Document Type: Conference Paper

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