A novel simulation fault injection method for dependability analysis

IEEE Design and Test of Computers

Volumn 26, Issue 6, 2009, Pages 50-60

  Lee, Dongwoo ^a   Na, Jongwhoa ^a  

^a Hankuk Aviation University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT SIMULATION; DEPENDABILITY ANALYSIS; FAULT INJECTION; FAULT LOCATION; FAULT TIME; HARDWARE DESIGN; LOG FILE; MIXED SIMULATION; RANDOM FAULTS; RUN-TIME EXECUTION; STORAGE SPACES; SYSTEM SIMULATIONS; SYSTEMC; TARGET HARDWARE; THREE STAGES; VULNERABLE AREA;

LOGIC DESIGN;

SOFTWARE TESTING;

EID: 73249140811     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2009.135     Document Type: Article

References (12)

1. C. E. Stroud, "Reliability of Majority Voting Based VLSI Fault-Tolerant Circuits", IEEE Trans. Very Large Scale Integration Systems, vol. 2, no. 4, 1994, pp. 516-521.
2. I. Koren and C. M. Krishna, Fault-Tolerant Systems, Morgan Kaufmann, 2007.
3. IEEE Std. 1633, IEEE Recommended Practice on Software Reliability, IEEE, 2008.
4. J. Arlat et al., "Fault Injection for Dependability Validation-A Methodology and Some Applications", IEEE Trans. Software Eng., vol. 16, no. 2, 1990, pp. 166-182.
5. D. Gil et al., "VHDL Simulation-Based Fault Injection Techniques", Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, A. Benso and P. Prinetto, eds., Kluwer Academic Publishers, 2003, pp. 159-176.
6. A. Benso and P. Prinetto, eds., Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, Kluwer Academic Publishers, 2003.
7. V. Krishnaswamy, J. Casas, and T. Tetzlaff, "A Switch Level Fault Simulation Environment", Proc. 37th Ann. Design Automation Conf. (DAC 00), ACM Press, 2000, pp. 780-785.
8. S. Z. Shazli and M. B. Tahoori, "Obtaining Microprocessor Vulnerability Factor Using Formal Methods", IEEE Int'l Symp. Defect and Fault Tolerance of VLSI Systems, IEEE Press, 2008, pp. 63-71.
9. D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann, 2005.
10. S. Mukherjee, Architecture Design for Soft Errors, Morgan Kaufmann, 2007, pp. 149-150, 154.
11. B. W. Johnson, Design and Analysis of Fault Tolerant Digital Systems, Addison-Wesley, 1989, pp. 169-175.
12. J. Yoo, "Harnessing Checker Hierarchy for Reliable Microprocessors", doctoral dissertation, ECE Dept., Univ. of Maryland, 2007, pp. 84-88.