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1
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84971277833
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Detailed comparison of dependability analyses performed at RT and gate levels
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Cambridge, Boston, MA, USA, Nov.
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A. Ammari, R. Leveugle, M. Sonza-Reorda, and M. Violante, "Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels," in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, Boston, MA, USA, Nov. 2003, pp. 336-343.
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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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Ammari, A.1
Leveugle, R.2
Sonza-Reorda, M.3
Violante, M.4
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2
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84893748923
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New techniques for speeding up fault-injection campaigns
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March
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L. Berrojo, I. Gonzalez, F. Corno, M. Sonza-Reorda, G. Squillero, L. Entrena, and C. Lopez, "New Techniques for Speeding up Fault-Injection Campaigns," Design, Automation and Test in Eumpe Conference (DATE), March 2002, pp. 847-852.
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Design, Automation and Test in Eumpe Conference (DATE)
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Berrojo, L.1
Gonzalez, I.2
Corno, F.3
Sonza-Reorda, M.4
Squillero, G.5
Entrena, L.6
Lopez, C.7
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3
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84962664102
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Bit-flip injection in processor-based archi tectures: A case study
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Isle of Bendor, France, July
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G.C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, and R. Velazco, "Bit-Flip Injection in Processor-Based Archi tectures: A Case Study," 8th IEEE International On-line Testing Workshop, Isle of Bendor, France, July 2002, pp. 117-127.
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(2002)
8th IEEE International On-line Testing Workshop
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Cardarilli, G.C.1
Kaddour, F.2
Leandri, A.3
Ottavi, M.4
Pontarelli, S.5
Velazco, R.6
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4
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0035193910
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Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits
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San Francisco, California, USA, Oct.
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P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and A. Violante, "Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits," in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 2001, pp. 250-258.
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(2001)
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
, pp. 250-258
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Civera, P.1
Macchiarulo, L.2
Rebaudengo, M.3
Sonza Reorda, M.4
Violante, A.5
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5
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0035202381
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Comparison and application of different VHDL-based fault injection techniques
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San Francisco, California, USA, Oct.
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J. Gracia, J.C. Baraza, D. Gil, and P.J. Gil, "Comparison and Application of Different VHDL-Based Fault Injection Techniques," in IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 2001, pp. 233-241.
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(2001)
IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems
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Gracia, J.1
Baraza, J.C.2
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6
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33645442746
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http://www.8051.free.fr/
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7
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0034517345
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Fault injection in VHDL descriptions and emulation
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Yamanashi, Japan, Oct.
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R. Leveugle, "Fault Injection in VHDL Descriptions and Emulation," in IEEE International Symposium on Defect and Fault Tolerance, in VLSI Systems, Yamanashi, Japan, Oct. 2000, pp. 414-419.
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(2000)
IEEE International Symposium on Defect and Fault Tolerance, in VLSI Systems
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Leveugle, R.1
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8
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84962759345
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Multi-level fault injection experiments based on VHDL descriptions: A case study
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Isle of Bendor, France, July
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R. Leveugle and K. Hadjiat, "Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study," 8th IEEE Int. On-Line Testing Workshop, Isle of Bendor, France, July 2002, pp. 107-111.
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(2002)
8th IEEE Int. On-line Testing Workshop
, pp. 107-111
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Leveugle, R.1
Hadjiat, K.2
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9
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0141630235
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Multi-level fault injections in VHDL descriptions: Alternative approaches and experiments
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R. Leveugle and K. Hadjiat, "Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments," Journal of Electronic Testing: Theory and Applications (JETTA), vol. 19, no. 5, pp. 559-575, 2003.
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Journal of Electronic Testing: Theory and Applications (JETTA)
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Leveugle, R.1
Hadjiat, K.2
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10
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0142206123
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Estimating circuit fault-tolerance by means of transient-fault injection in VHDL
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Palma de Mallorca, Spain, July
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F. Vargas, A. Amory, and R. Velazco, "Estimating circuit fault-tolerance by means of transient-fault injection in VHDL,"6th IEEE International On-Line. Testing Workshop, Palma de Mallorca, Spain, July 2000, pp. 67-72.
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(2000)
6th IEEE International On-Line. Testing Workshop
, pp. 67-72
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Vargas, F.1
Amory, A.2
Velazco, R.3
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