Error propagation analysis using FPGA-based SEU-fault injection

Microelectronics Reliability

Volumn 48, Issue 2, 2008, Pages 319-328

  Ejlali, Alireza ^a   Miremadi, Seyed Ghassem ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ERROR ANALYSIS; FAULT DETECTION; MICROELECTRONICS; PROBLEM SOLVING;

ERROR PROPAGATION ANALYSIS; FAULT INJECTION; FAULT TOLERANT SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 44249085379     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2007.04.003     Document Type: Article

References (27)

1. Aidemark J., Folkesson P., and Karlsson J. Path-based error coverage prediction. Journal of Electronic Testing Theory and Application (JETTA) 16 June (2002) 343-349
2. Ammari A, Hadjiat K, Leveugle R, On combining fault classification and error propagation analysis in RT-Level dependability evaluation. In:10th IEEE international on-line testing symposium (IOLTS) 2004; p. 227-32.
3. Antoni L., Leveugle R., and Fehér B. Using run-time reconfiguration for fault injection applications. IEEE Transactions on Instrumentation and Measurement 52 5 (2003) 1468-1473 October
4. Carreira J, Madeira H, Silva J, Xception: Software fault injection and monitoring in processor functional units. In: Conference on dependable computing for critical applications (DCCA-5); 1995. p. 135-49, September.
5. Civera P., Macchiarulo L., Rebaudengo M., Sonza Reorda M., and Violante M. Exploiting circuit emulation for fast hardness evaluation. IEEE Trans Nucl Sci 48 Dec (2001) 2210-2216
6. Dupont E., Nicolaidis M., and Rohr P. Embedded robustness IPs for transient-error-free ICs. IEEE Des Test Comput 19 3 (2002) 54-68 May-June
7. Ejlali A, Miremadi SG, FPGA-based fault injection into switch-level models. journal of microprocessors and microsystems, Elsevier Science. April 2004;28(5-6): p. 317-27.
8. Ejlali A, Miremadi SG, Zarandi HR, Asadi G, Sarmadi SB. A hybrid fault injection approach based on simulation and emulation co-operation. In: Proceedings of the IEEE/IFIP international conference on dependable systems and networks (DSN-2003), San Francisco, USA, June 2003; p. 479-88.
9. Ejlali A, Schmitz MT, Al-Hashimi BM, Miremadi SG, Rosinger P. Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. IEEE Trans (VLSI) Syst. April 2006;14(4):p. 323-35.
10. Folkesson P, Svensson S, Karlsson J. A comparison of simulation based and scan chain implemented fault injection. In: Proceedings of the 28th international symposium on fault-tolerant computing. 1998; p. 284-93.
11. Gonzales I, Berrojo L. Supporting fault tolerance in an industrial environment: The AMATISTA approach. In: Proceedings of the IEEE international on-line test workshop. 2001; p. 178-83.
12. .
13. .
14. .
15. Jenn E, Arlat J, Rimen M, Ohlsson J, Karlsson J. Fault injection into VHDL models: The MEFISTO tool. In: Proceedins of the 24th international symposium on fault-tolerant computing. 1994; p. 336-44.
16. Kim S, Somani AK. Soft error sensitivity characterization for microprocessor dependability enhancement strategy. In: Proceedings of the international conference on dependable systems and networks. June 2002; p. 416-25.
17. Leveugle R, Fault injection in VHDL descriptions and emulation. In: Proceedings. IEEE international symposium on defect and fault tolerance in VLSI systems. Oct. 2000; p. 414-19.
18. Leveugle R, Ammari A. Early SEU fault injection in digital, analog and mixed signal circuits: a global flow Design. In: Proceedings of the design, automation and test in europe conference and exhibition, Febuary 2004, vol. 1, p. 590-95.
19. Lima F, Rezgui S, Carro L, Velazco R, Reis R. On the use of VHDL simulation and emulation to derive error rates. In: Sixth European conference on radiation and its effects on components and systems. September 2001; p. 253-60.
20. Maheshwari A., Burleson W., and Tessier R. Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans (VLSI) Syst 12 3 (2004) 299-311
21. Rezgui S., Swift G.M., Velazco R., and Farmanesh F.F. Validation of an SEU simulation technique for a complex processor: PowerPC7400. IEEE Trans Nucl Sci 49 6 (2002) 3156-3162 December
22. Shanbhag N.R. Reliable and efficient system-on-chip design. Computer 37 3 (2004) 42-50
23. Violante M. Accurate single-event-transient analysis via zero-delay logic simulation. IEEE Trans Nucl Sci 50 6 (2003) 2113-2118 December
24. Aguirre M, Tombs JN, Muñoz F, Baena V, Torralba A, Fernández-León A, Tortosa-López F. FT-UNSHADES: A new system for SEU Injection, analysis and diagnostics over post synthesis netlists, NASA Military and Aerospace Programmable Logic Devices (MAPLD 2005), Washington DC (USA), 2005.
25. Tombs J, Aguirre Echanóve MA, Muñoz F, Baena V, Torralba A, Fernández-León A, Tortosa F. The implementation of a FPGA hardware debugger system with minimal system overhead. In: Proceedings of the international conference on field programmable logic and application (FPL), Lecture Notes in Computer Science (LNCS). 2004. p. 1062-66.
26. Nguyen H.T., Yagil Y., Seifert N., and Reitsma M. Chip-level soft error estimation method. IEEE Trans. Device and Materials Reliability 5 3 (2005) 365-381
27. Civera P, Macchiarulo L, Rebaudengo M, Sonza Reorda M, Violante A, Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits. In: IEEE international symposium on defect and fault tolerance in VLSI systems, (DFT'01). 2001; p. 250-58.