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Volumn 4, Issue 1, 2013, Pages 22-41

A simulation-based framework for the exploration of mapping solutions on heterogeneous MPSoCs

Author keywords

Design Space Exploration; Heterogeneous Multi Processor Systems on Chip (Mpsocs); Mapping; Simulation; System C; Y Chart

Indexed keywords


EID: 84880441911     PISSN: 19473176     EISSN: 19473184     Source Type: Journal    
DOI: 10.4018/jertcs.2013010102     Document Type: Article
Times cited : (2)

References (23)
  • 1
    • 33847264056 scopus 로고    scopus 로고
    • Efficient architecture/compiler co-exploration using analytical models
    • Springer. doi:10.1007/s10617-006-9588-7
    • Agosta, G., Palermo, G., & Silvano, C. (2007). Efficient architecture/compiler co-exploration using analytical models. [Springer.]. Design Automation for Embedded Systems, 11(1), 1-23. doi:10.1007/s10617-006- 9588-7.
    • (2007) Design Automation for Embedded Systems , vol.11 , Issue.1 , pp. 1-23
    • Agosta, G.1    Palermo, G.2    Silvano, C.3
  • 2
    • 70450278794 scopus 로고    scopus 로고
    • ReSP: A nonintrusive transaction-level reflective MPSoC simulation platform for design space exploration
    • doi:10.1109/TCAD.2009.2030268
    • Beltrame, G., Fossati, L., & Sciuto, D. (2009). ReSP: A nonintrusive transaction-level reflective MPSoC simulation platform for design space exploration. IEEE Transactions on CAD of Integrated Circuits and Systems, 28(12), 1857-1869. doi:10.1109/TCAD.2009.2030268.
    • (2009) IEEE Transactions on CAD of Integrated Circuits and Systems , vol.28 , Issue.12 , pp. 1857-1869
    • Beltrame, G.1    Fossati, L.2    Sciuto, D.3
  • 3
    • 77953825588 scopus 로고    scopus 로고
    • Decision-theoretic design space exploration of multiprocessor platforms
    • doi:10.1109/TCAD.2010.2049053
    • Beltrame, G., Fossati, L., & Sciuto, D. (2010). Decision-theoretic design space exploration of multiprocessor platforms. IEEE Transactions on CAD of Integrated Circuits and Systems, 29(7), 1083-1095. doi:10.1109/TCAD.2010. 2049053.
    • (2010) IEEE Transactions on CAD of Integrated Circuits and Systems , vol.29 , Issue.7 , pp. 1083-1095
    • Beltrame, G.1    Fossati, L.2    Sciuto, D.3
  • 5
    • 84865223038 scopus 로고    scopus 로고
    • Automatic abstraction of RTL IPs into equivalent TLM descriptions
    • doi:10.1109/TC.2010.187
    • Bombieri, N., Fummi, F., & Pravadelli, G. (2011). Automatic abstraction of RTL IPs into equivalent TLM descriptions. IEEE Transactions on Computers, 60(12), 1730-1743. doi:10.1109/TC.2010.187.
    • (2011) IEEE Transactions on Computers , vol.60 , Issue.12 , pp. 1730-1743
    • Bombieri, N.1    Fummi, F.2    Pravadelli, G.3
  • 7
    • 77952945784 scopus 로고    scopus 로고
    • Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems
    • doi:10.1109/TCAD.2010.2048354
    • Ferrandi, F., Lanzi, P. L., Pilato, C., Sciuto, D., & Tumeo, A. (2010). Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems. IEEE Transactions on CAD of Integrated Circuits and Systems, 29(6), 911-924. doi:10.1109/TCAD.2010.2048354.
    • (2010) IEEE Transactions on CAD of Integrated Circuits and Systems , vol.29 , Issue.6 , pp. 911-924
    • Ferrandi, F.1    Lanzi, P.L.2    Pilato, C.3    Sciuto, D.4    Tumeo, A.5
  • 8
    • 9644281035 scopus 로고    scopus 로고
    • Methods for evaluating and covering the design space during early design development
    • Gries, M. (2004). Methods for evaluating and covering the design space during early design development. Integration, the VLSI Journal, 38(2), 131-183.
    • (2004) Integration, the VLSI Journal , vol.38 , Issue.2 , pp. 131-183
    • Gries, M.1
  • 10
    • 84860271429 scopus 로고    scopus 로고
    • OSCAR: An optimization methodology exploiting spatial correlation in multi-core design spaces
    • doi:10.1109/TCAD.2011.2177457
    • Mariani, G., Palermo, G., Silvano, C., & Zaccaria, V. (2012). OSCAR: An optimization methodology exploiting spatial correlation in multi-core design spaces. IEEE Transactions on CAD of Integrated Circuits and Systems, 21(5), 740-753. doi:10.1109/TCAD.2011.2177457.
    • (2012) IEEE Transactions on CAD of Integrated Circuits and Systems , vol.21 , Issue.5 , pp. 740-753
    • Mariani, G.1    Palermo, G.2    Silvano, C.3    Zaccaria, V.4
  • 12
    • 33744721815 scopus 로고    scopus 로고
    • A systematic approach to exploring embedded system architectures at multiple abstraction levels
    • doi:10.1109/TC.2006.16
    • Pimentel, A., Erbas, C., & Polstra, S. (2006). A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers, 55(2), 99-112. doi:10.1109/TC.2006.16.
    • (2006) IEEE Transactions on Computers , vol.55 , Issue.2 , pp. 99-112
    • Pimentel, A.1    Erbas, C.2    Polstra, S.3
  • 13
    • 84880409844 scopus 로고    scopus 로고
    • Politecnico di Milano Retrieved March 12 2013
    • Politecnico di Milano. (2009). ReSP web site. Retrieved March 12, 2013, from http://code.google.com/p/resp-sim/.
    • (2009)
  • 14
    • 84880443360 scopus 로고    scopus 로고
    • Politecnico di Milano Retrieved March 12 2013
    • Politecnico di Milano. (2012). Panda web site. Retrieved March 12, 2013, from http://panda.dei.polimi.it.
    • (2012)
  • 15
    • 84893745478 scopus 로고    scopus 로고
    • Flexible and formal modeling of microprocessors with application to retargetable simulation
    • Qin, W., & Malik, S. (2003). Flexible and formal modeling of microprocessors with application to retargetable simulation. In Proceedings of the Design, Automation & Test in Europe (DATE) (pp. 556-561.
    • (2003) Proceedings of the Design, Automation & Test in Europe (DATE , pp. 556-561
    • Qin, W.1    Malik, S.2
  • 17
    • 0035509391 scopus 로고    scopus 로고
    • Platform-based design and software design methodology for embedded systems
    • doi:10.1109/54.970421
    • Sangiovanni-Vincentelli, A., & Martin, G. (2001). Platform-based design and software design methodology for embedded systems. IEEE Design & Test of Computers, 18(6), 23-33. doi:10.1109/54.970421.
    • (2001) IEEE Design & Test of Computers , vol.18 , Issue.6 , pp. 23-33
    • Sangiovanni-Vincentelli, A.1    Martin, G.2
  • 18
    • 0036949142 scopus 로고    scopus 로고
    • OpenMP: Parallel programming API for shared memory multiprocessors and on-chip multiprocessors
    • Sato, M. (2002). OpenMP: Parallel programming API for shared memory multiprocessors and on-chip multiprocessors. In Proceedings of the International Symposium on System Synthesis (ISSS) (pp. 109-111)..
    • (2002) Proceedings of the International Symposium on System Synthesis (ISSS , pp. 109-111
    • Sato, M.1
  • 19
    • 84880411272 scopus 로고    scopus 로고
    • Platform architect web site, Retrieved March 12 2013
    • Synopsys (2012). Platform architect web site. Retrieved March 12, 2013, from http://www.synopsys.com/Systems/ArchitectureDesign.
    • (2012)
  • 20
    • 84880438415 scopus 로고    scopus 로고
    • Univ. de Bretagne-Sud Retrieved March 12 2013
    • Univ. de Bretagne-Sud. (2006). GAUT-High-level synthesis tool from C to RTL web page. Retrieved March 12, 2013, from http://www-labsticc.univ-ubs.fr/ www-gaut/.
    • (2006) GAUT-High-level Synthesis Tool from C to RTL Web Page
  • 21
    • 84880444907 scopus 로고    scopus 로고
    • Univ. of Wisconsin et al Retrieved March 12 2011
    • Univ. of Wisconsin et al. (2011). Gem5 simulator system web site. Retrieved March 12, 2013, from http://www.m5sim.org/.
    • (2013) Gem5 Simulator System Web Site
  • 22
    • 84880431247 scopus 로고    scopus 로고
    • Univ. Pierre et Marie Curie Retrieved March 12 2009
    • Univ. Pierre et Marie Curie. (2009). SoCLib web site. Retrieved March 12, 2013, from http://www.soclib.fr/.
    • (2013)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.