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Volumn 2, Issue 2, 2012, Pages 278-294

Swizzle-switch networks for many-core systems

Author keywords

Crossbars; manycore systems; multicore processing; network topology; network on chip; on chip interconnects; parallel architectures

Indexed keywords

CROSSBARS; MANY-CORE; MULTI CORE; NETWORK ON CHIP; NETWORK TOPOLOGY; ON-CHIP INTERCONNECTS;

EID: 84862310416     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2012.2193936     Document Type: Article
Times cited : (73)

References (52)
  • 2
    • 33645977177 scopus 로고    scopus 로고
    • Xbox 360 system arch
    • Mar./Apr.
    • J. Andrews and N. Baker, "Xbox 360 system arch," IEEE Micro, vol. 26, no. 2, pp. 25-37, Mar./Apr. 2006.
    • (2006) IEEE Micro , vol.26 , Issue.2 , pp. 25-37
    • Andrews, J.1    Baker, N.2
  • 3
    • 84862319753 scopus 로고    scopus 로고
    • Cortex-a5 processor
    • ARM Ltd
    • ARM Ltd, Cortex-A5 Processor, ARM Databrief 2010.
    • (2010) ARM Databrief
  • 4
    • 34547471544 scopus 로고    scopus 로고
    • Design tradeoffs for tiled CMP on-chip networks
    • DOI 10.1145/1183401.1183430, Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006
    • J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP on-chip networks," in Proc. 20th Annu. Int. Conf. Supercomput., 2006, pp. 187-198. (Pubitemid 47168505)
    • (2006) Proceedings of the International Conference on Supercomputing , pp. 187-198
    • Balfour, J.1    Dally, W.J.2
  • 7
    • 33745800231 scopus 로고    scopus 로고
    • A survey of research and practices of network-on-chip
    • T. Bjerregaard and S. Mahadevan, "A survey of research and practices of network-on-chip," in ACM Comput. Surv., 2006.
    • (2006) ACM Comput. Surv.
    • Bjerregaard, T.1    Mahadevan, S.2
  • 8
    • 34047104005 scopus 로고    scopus 로고
    • Simulation and analysis of network-on-chip architectures: Ring, spidergon and 2-D mesh
    • L. Bononi and N. Concer, "Simulation and analysis of network-on-chip architectures: Ring, spidergon and 2-D mesh," in Proc. Design, Automat. Test Eur., 2006, vol. 2, p. 6.
    • (2006) Proc. Design, Automat. Test Eur. , vol.2 , pp. 6
    • Bononi, L.1    Concer, N.2
  • 9
    • 44149099405 scopus 로고    scopus 로고
    • Noc topologies exploration based on mapping and simulation models
    • Methods Tools
    • L. Bononi and N. Concer et al., "Noc topologies exploration based on mapping and simulation models," in Proc. 10th Euromicro Conf. Digital Syst. Design Archit., Methods Tools, 2007, pp. 543-543.
    • (2007) Proc. 10th Euromicro Conf. Digital Syst. Design Archit , pp. 543-543
    • Bononi, L.1    Concer, N.2
  • 11
    • 33845889046 scopus 로고    scopus 로고
    • Interconnect-aware coherence protocols for chip multiprocessors
    • L. Cheng and N. Muralimanohar et al., "Interconnect-aware coherence protocols for chip multiprocessors," in Proc. 33rd Int. Symp. Comput. Archit., 2006, pp. 339-351.
    • (2006) Proc. 33rd Int. Symp. Comput. Archit. , pp. 339-351
    • Cheng, L.1    Muralimanohar, N.2
  • 14
    • 64949130713 scopus 로고    scopus 로고
    • Design and evaluation of a hierarchical on-chip interconnect for next-generation cmps
    • Feb.
    • R. Das and S. Eachempati et al., "Design and evaluation of a hierarchical on-chip interconnect for next-generation cmps," in Proc. IEEE 15th Int. Symp. High Performance Comput. Architect., Feb. 2009, pp. 175-186.
    • (2009) Proc. IEEE 15th Int. Symp. High Performance Comput. Architect , pp. 175-186
    • Das, R.1    Eachempati, S.2
  • 15
    • 84860678550 scopus 로고    scopus 로고
    • Centip3de: A 3930 dmips/w configurable near-threshold 3-D-stacked system w/64 arm cortex-m3 cores
    • Feb.
    • D. Fick and R. Dreslinski et al., "Centip3de: A 3930 dmips/w configurable near-threshold 3-D-stacked system w/64 arm cortex-m3 cores," in IEEE Int. Solid-State Circuits Conf. Dige. Tech. Papers, Feb. 2012, pp. 190-192.
    • (2012) IEEE Int. Solid-State Circuits Conf. Dige. Tech. Papers , pp. 190-192
    • Fick, D.1    Dreslinski, R.2
  • 16
    • 0030819327 scopus 로고    scopus 로고
    • Spider: A high-speed network interconnect
    • M. Galles, "Spider: A high-speed network interconnect," IEEE Micro, vol. 17, no. 1, pp. 34-39, Jan. 1997. (Pubitemid 127571630)
    • (1997) IEEE Micro , vol.17 , Issue.1 , pp. 34-39
    • Galles, M.1
  • 18
    • 76749160934 scopus 로고    scopus 로고
    • Preemptive virtual clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip
    • New York
    • B. Grot, S. W. Keckler, and O. Mutlu, "Preemptive virtual clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip," in Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchit., New York, 2009, pp. 268-279.
    • (2009) Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchit , pp. 268-279
    • Grot, B.1    Keckler, S.W.2    Mutlu, O.3
  • 19
    • 33646015987 scopus 로고    scopus 로고
    • Synergistic processing in cell's multicore architecture
    • Mar./Apr.
    • M. Gschwind and H. Hofstee et al., "Synergistic processing in cell's multicore architecture," IEEE Micro, vol. 26, no. 2, pp. 10-24, Mar./Apr. 2006.
    • (2006) IEEE Micro , vol.26 , Issue.2 , pp. 10-24
    • Gschwind, M.1    Hofstee, H.2
  • 22
    • 78650922410 scopus 로고    scopus 로고
    • A 48-core ia-32 message-passing processor with DVFs in 45 nm CMOS
    • Jan.
    • J. Howard and S. Dighe et al., "A 48-core ia-32 message-passing processor with DVFs in 45 nm CMOS," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 173-183, Jan. 2011.
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.1 , pp. 173-183
    • Howard, J.1    Dighe, S.2
  • 24
    • 85032776540 scopus 로고    scopus 로고
    • Intel atom processor for nettop platforms
    • Nov.
    • Intel Corp, Intel atom processor for nettop platforms, Intel product brief Nov. 2008.
    • (2008) Intel Product Brief
    • Corp, I.1
  • 25
    • 52649171528 scopus 로고    scopus 로고
    • Virtual circuit tree multicasting: A case for on-chip hardware multicast support
    • N. E. Jerger, L.-S. Peh, and M. Lipasti, "Virtual circuit tree multicasting: A case for on-chip hardware multicast support," in Proc. 35th Int. Symp. Computer Archit., 2008, pp. 229-240.
    • (2008) Proc. 35th Int. Symp. Computer Archit. , pp. 229-240
    • Jerger, N.E.1    Peh, L.-S.2    Lipasti, M.3
  • 26
    • 85027210913 scopus 로고    scopus 로고
    • An 8-core, 64-thread, 64-bit power efficient SPARC SOC (niagara2)
    • T. Johnson and U. Nawathe, "An 8-core, 64-thread, 64-bit power efficient SPARC SOC (niagara2)," in IEEE Int. Dig. Tech. Papers, Feb. 2007, pp. 108-590.
    • (2007) IEEE Int. Dig. Tech. Papers, Feb. , pp. 108-590
    • Johnson, T.1    Nawathe, U.2
  • 27
    • 0036949388 scopus 로고    scopus 로고
    • An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
    • DOI 10.1145/635508.605420
    • C. Kim, D. Burger, and S. W. Keckler, "An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches," in Proc. 10th Int. Conf. Architectural Support Programm. Languages Operat. Syst., 2002, pp. 211-222. (Pubitemid 44892235)
    • (2002) Operating Systems Review (ACM) , vol.36 , Issue.5 , pp. 211-222
    • Kim, C.1    Burger, D.2    Keckler, S.W.3
  • 31
    • 34547996037 scopus 로고    scopus 로고
    • Bcb: A buffered crossbar switch fabric utilizing shared memory
    • Methods Tools
    • G. Kornaros, "Bcb: A buffered crossbar switch fabric utilizing shared memory," in Proc. 9th EUROMICRO Conf. Dig. Syst. Design: Archit., Methods Tools, 2006, pp. 180-188.
    • (2006) Proc. 9th EUROMICRO Conf. Dig. Syst. Design: Archit , pp. 180-188
    • Kornaros, G.1
  • 32
    • 27544456315 scopus 로고    scopus 로고
    • Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling
    • Proceedings - 32nd International Symposium on Computer Architecture, ISCA 2005
    • R. Kumar, V. Zyuban, and D. M. Tullsen, "Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling," in Proc. 32nd Int. Symp. Comput. Archit., Jun. 2005, pp. 408-419. (Pubitemid 41543458)
    • (2005) Proceedings - International Symposium on Computer Architecture , pp. 408-419
    • Kumar, R.1    Zyuban, V.2    Tullsen, D.M.3
  • 33
    • 52649094492 scopus 로고    scopus 로고
    • Globally-synchronized frames for guaranteed quality-of-service in on-chip networks
    • Jun.
    • J. W. Lee, M. C. Ng, and K. Asanovic, "Globally-synchronized frames for guaranteed quality-of-service in on-chip networks," in Proc. 35th Int. Symp. Comput. Archit., Jun. 2008, pp. 89-100.
    • (2008) Proc. 35th Int. Symp. Comput. Archit , pp. 89-100
    • Lee, J.W.1    Ng, M.C.2    Asanovic, K.3
  • 34
    • 35348895370 scopus 로고    scopus 로고
    • Ccc: Crossbar connected caches for reducing energy consumption of on-chip multiprocessors
    • Sep.
    • L. Li et al., "Ccc: Crossbar connected caches for reducing energy consumption of on-chip multiprocessors," in Proc. Euromicro Symp. Digital Syst. Design, Sep. 2003, pp. 41-48.
    • (2003) Proc. Euromicro Symp. Digital Syst. Design , pp. 41-48
    • Li, L.1
  • 35
    • 35348900723 scopus 로고    scopus 로고
    • Virtual hierarchies to support server consolidation
    • DOI 10.1145/1250662.1250670, ISCA'07: 34th Annual International Symposium on Computer Architecture, Conference Proceedings
    • M. R. Marty and M. D. Hill, "Virtual hierarchies to support server consolidation," in Proc. 34th Annu. Int. Symp. Comput. Archit., 2007, pp. 46-56. (Pubitemid 47582090)
    • (2007) Proceedings - International Symposium on Computer Architecture , pp. 46-56
    • Marty, M.R.1    Hill, M.D.2
  • 36
    • 0032655137 scopus 로고    scopus 로고
    • The ISLIP scheduling algorithm for input-queued switches
    • Apr.
    • N. McKeown, "The ISLIP scheduling algorithm for input-queued switches," IEEE/ACM Trans. Network., vol. 7, no. 2, pp. 188-201, Apr. 1999.
    • (1999) IEEE/ACM Trans. Network. , vol.7 , Issue.2 , pp. 188-201
    • McKeown, N.1
  • 40
    • 77952016604 scopus 로고    scopus 로고
    • An analysis of on-chip interconnection networks for large-scale chip multiprocessors
    • May
    • D. Sanchez, G. Michelogiannakis, and C. Kozyrakis, "An analysis of on-chip interconnection networks for large-scale chip multiprocessors," in ACM Trans. Archit. Code Optim., May 2010, pp. 4:1-4:28.
    • (2010) ACM Trans. Archit. Code Optim , vol.1-4 , Issue.28 , pp. 4
    • Sanchez, D.1    Michelogiannakis, G.2    Kozyrakis, C.3
  • 41
    • 80052660751 scopus 로고    scopus 로고
    • Swift: A 2.1 tb/s 32 32 self-arbitrating manycore interconnect fabric
    • Jun.
    • S. Satpathy and R. Dreslinski et al., "Swift: A 2.1 tb/s 32 32 self-arbitrating manycore interconnect fabric," in Proc. 2011 Symp. VLSI Circuits, Jun. 2011, pp. 138-139.
    • (2011) Proc. 2011 Symp. VLSI Circuits , pp. 138-139
    • Satpathy, S.1    Dreslinski, R.2
  • 42
    • 77957996907 scopus 로고    scopus 로고
    • A 1.07 tbit/s 128 128 swizzle network for SIMD processors
    • Jun.
    • S. Satpathy and Z. Foo et al., "A 1.07 tbit/s 128 128 swizzle network for SIMD processors," in IEEE Symp. VLSI Circuits, Jun. 2010, pp. 81-82.
    • (2010) IEEE Symp. VLSI Circuits , pp. 81-82
    • Satpathy, S.1    Foo, Z.2
  • 43
    • 84860653566 scopus 로고    scopus 로고
    • A 4.5 tb/s 3.4 tb/s/w 64 64 switch fabric with self-updating least recently granted priority and quality of service arbitration in 45 nm CMOS
    • Feb.
    • S. Satpathy and K. Sewell et al., "A 4.5 tb/s 3.4 tb/s/w 64 64 switch fabric with self-updating least recently granted priority and quality of service arbitration in 45 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers., Feb. 2012, pp. 478-480.
    • (2012) IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , pp. 478-480
    • Satpathy, S.1    Sewell, K.2
  • 45
    • 49249086142 scopus 로고    scopus 로고
    • Larrabee: A many-core 86 architecture for visual computing
    • L. Seiler and D. E. A. Carmean, "Larrabee: A many-core 86 architecture for visual computing," in ACM Trans. Graphics, 2008.
    • (2008) ACM Trans. Graphics
    • Seiler, L.1    Carmean, D.E.A.2
  • 47
    • 76749118993 scopus 로고    scopus 로고
    • A performance evaluation of 2-D-mesh, ring, and crossbar interconnects for chip multi-processors
    • Dec.
    • J. C. Villanueva et al., "A performance evaluation of 2-D-mesh, ring, and crossbar interconnects for chip multi-processors," in Proc. 2nd Int. Workshop Network Chip Archit., Dec. 2009, pp. 51-56.
    • (2009) Proc. 2nd Int. Workshop Network Chip Archit , pp. 51-56
    • Villanueva, J.C.1
  • 48
    • 0037225560 scopus 로고    scopus 로고
    • A power model for routers: Modeling alpha 21364 and infiniband routers
    • Jan./Feb.
    • H.-S. Wang, L.-S. Peh, and S. Malik, "A power model for routers: Modeling alpha 21364 and infiniband routers," IEEE Micro, vol. 23, no. 1, pp. 26-35, Jan./Feb. 2003.
    • (2003) IEEE Micro , vol.23 , Issue.1 , pp. 26-35
    • Wang, H.-S.1    Peh, L.-S.2    Malik, S.3
  • 50
    • 0029179077 scopus 로고
    • The SPLASH-2 programs: Characterization and methodological considerations
    • Jun.
    • S. C. Woo and M. Ohara et al., "The SPLASH-2 programs: Characterization and methodological considerations," in Proc. 22nd Annu. Int. Symp. Comput. Archit., Jun. 1995, pp. 24-36.
    • (1995) Proc. 22nd Annu. Int. Symp. Comput. Archit , pp. 24-36
    • Woo, S.C.1    Ohara, M.2
  • 52
    • 33847112910 scopus 로고    scopus 로고
    • A study of the on-chip interconnection network for the IBM cyclops64 multi-core architecture
    • Apr.
    • Y. P. Zhang et al., "A study of the on-chip interconnection network for the IBM cyclops64 multi-core architecture," in Proc. 20th Int. Parallel Distrib. Process. Symp., Apr. 2006, p. 10.
    • (2006) Proc. 20th Int. Parallel Distrib. Process. Symp , pp. 10
    • Zhang, Y.P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.