Power and performance comparison of crossbars and buses as on-chip interconnect structures

Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers

Volumn 1, Issue , 1999, Pages 378-383

  Zhang, Yan ^b   Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; ENERGY UTILIZATION; TRANSISTORS;

DELAY PERFORMANCE; GLOBAL INTERCONNECT DELAY; INTERCONNECT STRUCTURES; MULTIPLE INPUTS; ON CHIP INTERCONNECT; PERFORMANCE COMPARISON; SYSTEMS-ON-A CHIPS; TRANSISTOR LEVEL;

INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT LAYOUT;

DATAPATH INTERCONNECTS;

EID: 0033345970     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.1999.832356     Document Type: Conference Paper

References (12)

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