Larrabee: A many-core x86 architecture for visual computing

ACM Transactions on Graphics

Volumn 27, Issue 3, 2008, Pages

  Seiler, Larry ^a   Carmean, Doug ^a   Sprangle, Eric ^a   Forsyth, Tom ^a   Abrash, Michael ^b   Dubey, Pradeep ^a   Junkins, Stephen ^a   Lake, Adam ^a   Sugerman, Jeremy ^c   Cavin, Robert ^a   Espasa, Roger ^a   Grochowski, Ed ^a   Juan, Toni ^a   Hanrahan, Pat ^c  

^a INTEL CORPORATION   (United States)

^b RAD Game Tools ^*

^c STANFORD UNIVERSITY   (United States)

Author keywords

GPGPU; Graphics architecture; Many core computing; Parallel processing; Realtime graphics; SIMD; Software rendering; Throughput computing; Visual computing

Indexed keywords

PIPELINE CODES; PIPELINES; STANDARDS;

APPLICATIONS.; CPU CORES; GPGPU; GRAPHICS ARCHITECTURE; LOGIC BLOCKS; MANY-CORE COMPUTING; OUT-OF-ORDER; PARALLEL PROCESSING; PARALLEL WORKLOADS; PERFORMANCE ANALYSES; PROGRAMMABILITY; PROGRAMMING MODELS; REALTIME GRAPHICS; SIMD; SOFTWARE RENDERING; THROUGHPUT COMPUTING; VISUAL COMPUTING;

LEARNING SYSTEMS;

EID: 49249086142     PISSN: 07300301     EISSN: 15577368     Source Type: Journal    
DOI: 10.1145/1360612.1360617     Document Type: Article

References (58)

1. AKENINE-MÖLLER, T., HAINES, E. 2002. Real-Time Rendering. 2nd Edition. A. K. Peters.
2. AILA, T., LAINE, S. 2004. Alias-Free Shadow Maps. In Proceedings of Eurographics Symposium on Rendering 2004, Eurographics Association. 161-166.
3. ALPERT, D., AVNON, D. 1993. Architecture of the Pentium Microprocessor. IEEE Micro, v.13, n.3, 11-21. May 1993.
4. AMD. 2007. Product description, web site: ati.amd.com/products/ Radeonhd3800/specs.html.
5. BADER, A., CHHUGANI, J., DUBEY, P., JUNKINS, S., MORRISON T., RAGOZIN, D., SMELYANSKIY. 2008. Game Physics Performance On Larrabee Architecture. Intel whitepaper, available in August, 2008. Web site: techresearch.intel.com.
6. BAVOIL, L., CALLAHAN, S., LEFOHN, A., COMBA, J. SILVA, C. 2007. Multi-fragment effects on the GPU using the k-buffer. In Proceedings of the 2007 Symposium on Interactive 3D Graphics and Games (Seattle, Washington, April 30 - May 02, 2007). I3D 2007. ACM, New York, NY, 97-104.
7. BLUMOFE, R., JOERG, C., KUSZMAUL, B., LEISERSON, C., RANDALL, K., ZHOU, Y. Aug. 25, 1996. Cilk: An Efficient Multithreaded Runtime System. Journal of Parallel and Distributed Computing, v. 37, i. 1, 55-69.
8. BLYTHE, D. 2006. The Direct3D 10 System. ACM Transactions on Graphics, 25, 3, 724-734.
9. BOOKOUT, D. July, 2007. Shadow Map Aliasing. Web site: www.gamedev.net/reference/articles/arti.cle2376.asp.
10. BUCK, I., FOLEY, T., HORN, D., SUGERMAN, J., FATAHALIAN, K., HOUSTON, M., AND HANRAHAN, P. 2004. Brook for GPUs: stream computing on graphics hardware. ACM Transactions on Graphics, v. 23, n. 3, 777-786.
11. CALLAHAN, S., IKITS, M., COMBA, J., SILVA, C. 2005. Hardware-assisted visibility sorting for unstructured volume rendering. IEEE Transactions on Visualization and Computer Graphics, 11, 3, 285-295
12. CHANDRA, R., MENON, R., DAGUM, L., KOHR, D, MAYDAN, D., MCDONALD, J. 2000. Parallel Programming in OpenMP. Morgan Kaufman.
13. CHEN, M., STOLL, G., IGEHY, H., PROUDFOOT, K., HANRAHAN P. 1998. Simple models of the impact of overlap in bucket rendering. In Proceedings of the ACM SIGGRAPH / EUROGRAPHICS Workshop on Graphics Hardware (Lisbon, Portugal, August 31 - September 01, 1998). S. N. Spencer, Ed. HWWS '98. ACM, New York, NY, 105-112.
14. CHEN, Y., CHHUGANI, J., DUBEY, P., HUGHES, C., KIM, D., KUMAR, S., LEE, V., NGUYEN A., SMELYANSKIY, M. 2008. Convergence of Recognition, Mining, and Synthesis Workloads and its Implications. In Procedings of IEEE, v. 96, n. 5, 790-807.
15. CHUVELEV, M., GREER, B., HENRY, G., KUZNETSOV, S., BURYLOV, I., SABANIN, B. Nov. 2007. Intel Performance Libraries: Multi-core ready Software for Numeric Intensive Computation. Intel Technology Journal, v. 11, i. 4, 1-10.
16. COHEN, J., LIN., M., MANOCHA, D., PONAMGI., D. 1995. I-COLLIDE: An Interactive and Exact Collision Detection System for Large-Scale Environments. In Proceedings of 1995 Symposium on Interactive 3D Graphics. SI3D '95. ACM, New York, NY, 189-196.
17. ELDRIDGE, M. 2001. Designing Graphics Architectures Around Scalability and Communication. PhD thesis, Stanford.
18. FOLEY, J., VAN DAM, A., FEINER, S., HUGHES, J. 1996. Computer Graphics: Principles and Practice. Addison Wesley.
19. FUCHS, H., POULTON, J., EYLES, J., GREER, T., GOLDFEATHER, J., ELLSWORTH, D., MOLNAR, S., TURK, G., TEBBS, B., ISRAEL, L. 1989. Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories. In Computer Graphics (Proceedings of ACM SIGGRAPH89), ACM, 79-88.
20. GHULOUM, A., SMITH, T., WU, G., ZHOU, X., FANG, J., GUO, P., SO, B., RAJAGOPALAN, M., CHEN, Y., CHEN, B. November 2007. Future-Proof Data Parallel Algorithms and Software on Intel Multi-Core Architectures. Intel Technology Journal, v. 11, i. 04, 333-348.
21. GILBERT, E., JOHNSON, D., KEERTHI, S. 1988. A fast procedure for computing the distance between complex objects in three-dimensional space. IEEE Journal of Robotics and Automation, 4, 2, 193-203.
22. GPGPU. 2007. GPGPU web site: www.gpgpu.org.
23. GREENE, N. 1996. Hierarchical polygon tiling with coverage masks, In Proceedings of ACM SIGGRAPH 93, ACM Press/ACM SIGGRAPH, New York, NY, Computer Graphics Proceedings, Annual Conference Series, ACM, 65-64.
24. GROCHOWSKI, E., RONEN, R., SHEN, J., WANG, H. 2004. Best of Both Latency and Throughput. 2004 IEEE International Conference on Computer Design (ICCD '04), 236-243.
25. GWENNAP, L. 1995. Intel's P6 Uses Decoupled Superscalar Design. Microprocessor Report, v. 9, n. 2, Feb. 16, 1995.
26. HSIEH, E., PENTKOVSKI, V., PIAZZA, T. 2001. ZR: A 3D API Transparent Technology For Chunk. Rendering. In Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture (Austin, Texas, December 01-05, 2001). International Symposium on Microarchitecture. IEEE Computer Society, Washington, DC, 284-291.
27. HUGHES, C. J., GRZESZCZUK, R., SIFAKIS, E., KIM, D., KUMAR, S., SELLE, A. P., CHHUGANI, J., HOLLIMAN, M., AND CHEN, Y. 2007. Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. In Proceedings of the 34th Annual international Symposium on Computer Architecture (San Diego, California, USA, June 09 -13, 2007). ISCA '07. ACM, New York, NY, 220-231.
28. IEEE Std. 1003.1, 2004 Edition. Standard for Information Technology - Portable Operating System Interface (POSIX) System Interfaces. The Open Group Technical Standard Base Specifications. Issue 6.
29. JACOBSEN, T. 2001. Advanced Character Physics. Proc. Game Developers Conference 2001, 1-10.
30. JOHNSON, G.S., LEE, J., BURNS, C.A., MARK, W.R. 2005. The irregular Z-buffer: Hardware acceleration for irregular data structures. ACM Transactions on Graphics. 24, 4, 1462-1482.
31. KELLEY, M., GOULD, K., PEASE, B., WINNER, S., YEN, A. 1994. Hardware accelerated rendering of CSG and transparency. In. Proceedings of SIGGRAPH 1994, ACM Press/ACM SIGGRAPH, New York, NY, Computer Graphics Proceedings, Annual Conference Series, ACM, 177-184.
32. KELLEY, M., WINNER, S., GOULD, K. 1992. A Scalable Hardware Render Accelerator using a Modified Scanline Algorithm. In Computer Graphics (Proceedings of ACM SIGGRAPH 1992), SIGGRAPH '92. ACM, New York, NY, 241-248.
33. KESSENICH, J., BALDWIN, D., ROST, R. The OpenGL Shading Language. Version 1.1. Sept. 7, 2006. Web site: www.opengl.org/registry/doc/GLSLangSpec.Full.1.20.8.pdf
34. KHAILANY, B., DALLY, W., RIXNER, S., KAPASI, U., MATTSON, P., NAMKOONG, J., OWENS, J., TOWLES, B., CHANG, A. 2001. Imagine: Media Processing with Streams. IEEE Micro, 21, 2, 35-46.
35. KONGETIRA, P., AINGARAN, K., OLUKOTUN, K. Mar/Apr 2005. Niagara: A 32-way multithreaded SPARC Processor. IEEE Micro. v. 25, i. 2. 21-29.
36. LAKE, A. 2005. Intel Graphics Media Accelerator Series 900 Developer's Guide. Version 2.0. Web site: download.intel.com/ids/gma/ Intel_915G_SDG_Feb05.pdf.
37. LLOYD, B., GOVINDARAJU, N., MOLNAR, S., MANOCHA, D. 2007. Practical logarithmic rasterization for low-error shadow maps. In Proceedings of the 22nd ACM SIGGRAPH/ EUROGRAPHICS Symposium on Graphics Hardware, 17-24.
38. MARK, W., GLANVILLE, S., AKELEY, K., KILGARD, M. 2003. Cg: A System for Programming Graphics Hardware in a C-like Language, ACM Transactions on Graphics, v. 22, n. 3, 896-907.
39. MICROSOFT. 2007. Microsoft Reference for HLSL. Web site: msdn2.microsoft.com/en-us/library/bb509638.aspx.
40. MOLNAR, S., COX, M., ELLSWORTH, D., AND FUCHS, H. 1994. A Sorting Classification of Parallel Rendering. IEEE Computer Graphics and Applications, v.14, n. 4, July 1994, 23-32.
41. MOLNAR, S., EYLES, J., POULTON, J. 1992. Pixelflow: High Speed Rendering Using Image Composition. Computer Graphics (Proceedings of SIGGRAPH 92), v. 26, n. 2, 231-240.
42. MOREIN, S. 2000. ATI Radeon HyperZ Technology. Presented at Graphics Hardware 2000. Web site: www.graphicshardware.org/previous/ www_2000/presentati.ons/ ATIHot3D.pdf.
43. NICKOLLS, J., BUCK, I., GARLAND, M. 2008. Scalable Parallel Programming with CUDA. ACM Queue, 6, 2, 40-53.
44. NVIDIA . 2008. Product description web site: www.nvidia.com/object/geforce_femily.html.
45. OWENS, J., LUEBKE, D., GOVINDARAJU, N., HARRIS, M., KRUGER, J., LEFOHN, A., PURCELL, T. 2007. A Survey of General Purpose Computation on Graphics Hardware. Computer Graphics Forum. v.26, n. 1, 80-113.
46. PHAM. D., ASANO, S., BOLLIGER.M., DAY, M., HOFSTEE, H., JOHNS., C., KAHLE, J., KAMEYAMA, A., KEATY, J., MASUBUCHI, Y., RILEY, M., SHIPPY, D., STASIASK, D., SUZUODI, M., WANG, M., WARNOCK, J., WEITZEL, S., WENDEL, D., YAMAZAKI, T., YAZAWA, K. 2005. The Design and Implementation of a First Generation CELL Processor. IEEE International Solid-State Circuits Conference. 184-186.
47. PHARR, M. 2006. Interactive Rendering in the Post-GPU Era. Presented at Graphics Hardware 2006. Web site: www.pharr.org/matt/.
48. PINEDA, J. 1988. A Parallel Algorithm for Polygon Rasterization. In Computer Graphics (Proceedings of ACM SIGGRAPH88), 22, 4, 17-20.
49. POWERVR. 2008. Web site: www.imgtec.com/powervr/products/ Graphics/in.dex.asp.
50. POLLACK, F. 1999. New Microarchitecture Challenges for the Coming Generations of CMOS Process Technologies. Micro32.
51. REINDERS, J., 2007. Intel Threading Building Blocks: Outfitting C++for Multi-core Processor Parallelism. O'Reily Media, Inc.
52. RESHETOV A., SOUPIKOV, A., HURLEY, J. 2005. Multi-level Ray Tracing Algorithm. ACM Transactions on Graphics, 24, 3, 1176-1185.
53. ROST, R. 2004. The OpenGL Shading Language. Addison Wesley.
54. SHEVTSOV, M., SOUPIKOV, A., KAPUSTIN, A. 2007. Ray-Triangle Intersection Algorithm for Modern CPU Architectures. In Proceedings of GraphiCon 2007, 33-39.
55. STEVENS, A. 2006. ARM Mali 3D Graphics System Solution. Web site: www.arm.com/miscPDFs/16514.pdf.
56. STOLL, G., ELDRIDGE, M., PATTERSON, D., WEBB, A., BERMAN, S., LEVY, R., CAYWOOD, C., TAVEIRA, M., HUNT, S., HANRAHAN, P. 2001. Lightning 2: A High Performance Display Subsystem for PC Clusters. In Computer Graphics (Proceedings of ACM SIGGRAPH 2001), ACM, 141-148.
57. TORBORG, J., KAJIYA, J. 1996. Talisman Commodity Realtime 3D Graphics for the PC. In Proceedings of ACM SIGGRAPH 1996, ACM Press/ACM SIGGRAPH, New York. Computer Graphics Proceedings, Annual Conference Series, ACM, 353-363.
58. WEXLER, D., GRITZ, L., ENDERTON, E., RICE, J. 2005. GPU-accelerated high-quality hidden surface removal. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware (Los Angeles, California, July 30-31, 2005). HWWS '05, ACM, New York, NY, 7-14.