A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors

2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42

Volumn , Issue , 2009, Pages 51-56

  Villanueva, Jesús Camacho ^a   Flich, José ^a   Duato, José ^a   Eberle, Hans ^b   Gura, Nils ^b   Olesinski, Wladek ^b  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b SUN MICROSYSTEMS   (United States)

Author keywords

Chip multi processors; Interconnects; Multiprocessor simulations; On chip networks

Indexed keywords

CACHE HIERARCHIES; CROSSBAR INTERCONNECTS; MULTI-PROCESSORS; MULTIPROCESSOR SIMULATION; NETWORK CONFIGURATION; NETWORK PARAMETERS; ON CHIP INTERCONNECT; ON CHIPS; ON-CHIP NETWORKS; OPERATING SYSTEMS; PERFORMANCE ANOMALY; PERFORMANCE EVALUATION; PROCESSING NODES; SIMULATION FRAMEWORK; SIMULATION MODEL; SYSTEM SIMULATOR; SYSTEM VARIABLES;

COMPUTER OPERATING SYSTEMS; EMBEDDED SYSTEMS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY;

COMPUTER SIMULATION;

EID: 76749118993     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1645213.1645226     Document Type: Conference Paper

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