Preemptive virtual clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 268-279

  Grot, Boris ^a   Keckler, Stephen W ^a   Mutlu, Onur ^b  

^a University of Texas at Austin   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

C.1.2 computer systems organization : multiprocessors interconnection architectures; Design; Measurement; Performance

Indexed keywords

ALGORITHMIC COMPLEXITY; ALLOCATION MECHANISM; BANDWIDTH PROVISIONING; CHIP MULTIPROCESSOR; COMPUTER SYSTEMS ORGANIZATION; EVALUATION METRICS; FAIRNESS GUARANTEE; INTERCONNECTION ARCHITECTURE; LINK SCHEDULING; MANY-CORE; MEMORY CONTROLLER; MULTIPLE APPLICATIONS; NETWORK BANDWIDTH; NETWORK-ON-A-CHIP; NETWORKS ON CHIPS; ON CHIPS; ON-CHIP NETWORKS; PACKET DELAY VARIATION; PREFERRED SOLUTIONS; PRIORITY INVERSION; PROCESSING ELEMENTS; SHARED RESOURCES; SOURCE NODES; SYSTEMS-ON-A-CHIP;

BANDWIDTH; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS;

PLASTIC PRODUCTS;

EID: 76749160934     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669149     Document Type: Conference Paper

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