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Volumn , Issue , 2007, Pages 543-546

NoC topologies exploration based on mapping and simulation models

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTERNET PROTOCOLS; MAPPING; NETWORK ARCHITECTURE; SYSTEMS ANALYSIS; TOPOLOGY;

EID: 44149099405     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2007.4341521     Document Type: Conference Paper
Times cited : (40)

References (20)
  • 1
    • 0036149420 scopus 로고    scopus 로고
    • Networks on Chips: A New SoC Paradigm
    • Jan
    • L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002.
    • (2002) Computer , vol.35 , Issue.1
    • Benini, L.1    De Micheli, G.2
  • 2
    • 47749145218 scopus 로고    scopus 로고
    • Networks on Chip, Eds. Jantsch, A. and Tenhunen, H. Kluwer Academic Publisher, 2003, ISBN: 1-4020-7392-5.
    • Networks on Chip, Eds. Jantsch, A. and Tenhunen, H. Kluwer Academic Publisher, 2003, ISBN: 1-4020-7392-5.
  • 3
    • 0034848112 scopus 로고    scopus 로고
    • Route Packets, Not Wires: On-Chip Interconnection Networks
    • W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. DAC Conf. 2001.
    • (2001) Proc. DAC Conf
    • Dally, W.J.1    Towles, B.2
  • 6
    • 47749090008 scopus 로고    scopus 로고
    • CoreConnect, www.ibm.com/chips/ products/coreconnect.
    • CoreConnect
  • 7
    • 0034995968 scopus 로고    scopus 로고
    • Evaluation of the traffic performance characteristics of SoC Communication Architectures
    • Bangalore
    • Lahiri, K., Raghunathan, A. and Dey, S. "Evaluation of the traffic performance characteristics of SoC Communication Architectures", in Proc. Conf. VLSI Design, Bangalore, 2001
    • (2001) Proc. Conf. VLSI Design
    • Lahiri, K.1    Raghunathan, A.2    Dey, S.3
  • 8
    • 0036505033 scopus 로고    scopus 로고
    • The Raw microprocessor: A computational fabric for software circuits and general-purpose programs
    • Taylor, M., Kim, J., Miller, J., Wentzlaff, D., et al., "The Raw microprocessor: a computational fabric for software circuits and general-purpose programs", IEEE Micro.2002.
    • (2002) IEEE Micro
    • Taylor, M.1    Kim, J.2    Miller, J.3    Wentzlaff, D.4
  • 9
    • 3042559894 scopus 로고    scopus 로고
    • xpipesCompiler: A tool for instantiating application specific Networks on Chip
    • Jalabert, A., Murali, S., Benini, L., and De Micheli, G., "xpipesCompiler: A tool for instantiating application specific Networks on Chip", in Proc. DATE Conf., 2004.
    • (2004) Proc. DATE Conf
    • Jalabert, A.1    Murali, S.2    Benini, L.3    De Micheli, G.4
  • 10
    • 21244433563 scopus 로고    scopus 로고
    • Spidergon: A novel on chip communication network
    • Tampere, Finland, Nov
    • M. Coppola et al. "Spidergon: a novel on chip communication network", proc. Int'l Symposium on System on Chip 2004, Tampere, Finland, Nov. 2004
    • (2004) proc. Int'l Symposium on System on Chip
    • Coppola, M.1
  • 11
    • 79960301858 scopus 로고    scopus 로고
    • Energy-performance aware mapping for regular NoC architectures
    • pp
    • Hu, J. and Marculescu, R. "Energy-performance aware mapping for regular NoC architectures", IEEE TCAD '05, pp.
    • IEEE TCAD '05
    • Hu, J.1    Marculescu, R.2
  • 12
    • 47749101990 scopus 로고    scopus 로고
    • SUNMAP: A tool for automatic topology selection and generation for
    • DAC04
    • Murali, De Micheli, G. "SUNMAP: A tool for automatic topology selection and generation for NoC", DAC04.
    • Murali, D.1    Micheli, G.2
  • 17
    • 47749084542 scopus 로고    scopus 로고
    • Mapping Heuristics and Simulation for NoC Topology Selection: A Case Study on Spidergon STNoC
    • tech. rep.t
    • L.Bononi, N.Concer,, M. Grammatikakis, "Mapping Heuristics and Simulation for NoC Topology Selection: A Case Study on Spidergon STNoC", tech. rep.t 2006
    • (2006)
    • Bononi, L.1    Concer, N.2    Grammatikakis, M.3
  • 18
    • 0038300184 scopus 로고    scopus 로고
    • A Progressive Approach to Handling Message-Dependent-Deadlock in Parallel Computer Systems
    • Y.H. Song, T.M. Prinkston "A Progressive Approach to Handling Message-Dependent-Deadlock in Parallel Computer Systems" IEEE Tran. On Par. and Dist. Sys. 2003
    • (2003) IEEE Tran. On Par. and Dist. Sys
    • Song, Y.H.1    Prinkston, T.M.2
  • 19
    • 34047104005 scopus 로고    scopus 로고
    • Simulation and Analysis of Network on Chip Architectures: Ring
    • L.Bononi, N.Concer "Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh" DATE 2006.
    • (2006) Spidergon and 2D Mesh
    • Bononi, L.1    Concer, N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.