Interconnect-aware coherence protocols for chip multiprocessors

Proceedings - International Symposium on Computer Architecture

Volumn 2006, Issue , 2006, Pages 339-350

  Liqun, Cheng ^a   Muralimanohar, Naveen ^a   Ramani, Karthik ^a   Balasubramonian, Rajeev ^a   Carter, John B ^a  

^a UNIVERSITY OF UTAH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN COMPLEXITY; INTELLIGENTLY MAPPING COHERENCE OPERATIONS; POWER-EFFICIENCY POTENTIAL;

BANDWIDTH; INTEGRATED CIRCUIT LAYOUT; NETWORK PROTOCOLS;

MICROPROCESSOR CHIPS;

EID: 33845889046     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2006.23     Document Type: Conference Paper

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