Flattened butterfly topology for on-chip networks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 172-182

  Kim, John ^a   Balfour, James ^a   Dally, William J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; ENERGY POLICY; OPTICAL INTERCONNECTS; TOPOLOGY; TWO DIMENSIONAL;

ENERGY CONSUMPTION; ENERGY CONSUMPTION.; HIGH-RADIX ROUTERS; IN-CHIP; INTERNATIONAL SYMPOSIUM; MESH NETWORKS; MICRO ARCHITECTURES; ON CHIP INTERCONNECTION NETWORKS; ON CHIP INTERCONNECTS; ON CHIP NETWORK (OCN); ON CHIPS; POWER CONSUMPTION (CE); SYNTHETIC TRAFFIC PATTERNS; VLSI LAYOUT;

INTERCONNECTION NETWORKS;

EID: 47349129525     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.29     Document Type: Conference Paper

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