A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Zhang, Ying Ping ^a   Jeong, Taikyeong ^a   Chen, Fei ^a   Wu, Haiping ^a   Nitzsche, Ronny ^a   Gao, Guang R ^a  

^a UNIVERSITY OF DELAWARE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER APPLICATIONS; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; SUPERCOMPUTERS; TELECOMMUNICATION TRAFFIC;

IBM CYCLOPS-64 (C64); LATENCY COMMUNICATION; ON-CHIP INTERCONNECTION NETWORK; SYSTEM-ON-A-CHIP;

INTERCONNECTION NETWORKS;

EID: 33847112910     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639301     Document Type: Conference Paper

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