Simulation and analysis of network on chip architectures: Ring, spidergon and 2D mesh

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 2, Issue , 2006, Pages

  Bononi, Luciano ^a   Concer, Nicola ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP ARCHITECTURES; PARALLEL COMPUTING SYSTEMS DESIGN; SPIDERGON TOPOLOGY; SYSTEMS ON CHIP (SOC);

COMPUTER SIMULATION; CONSTRAINT THEORY; MICROPROCESSOR CHIPS; THROUGHPUT; TOPOLOGY;

COMPUTER ARCHITECTURE;

EID: 34047104005     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269064     Document Type: Conference Paper

References (21)

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