An analysis of on-chip interconnection networks for large-scale chip multiprocessors

Transactions on Architecture and Code Optimization

Volumn 7, Issue 1, 2010, Pages

  Sanchez, Daniel ^a   Michelogiannakis, George ^a   Kozyrakis, Christos ^a  

^a Stanford University   (United States)

Author keywords

Chip multiprocessors; Hierarchical networks; Networks on chip

Indexed keywords

BANDWIDTH; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS; NETWORK-ON-CHIP;

ARCHITECTURAL LEVELS; CHIP MULTIPROCESSOR; HIERARCHICAL NETWORK; INTERCONNECTION-NETWORK; LARGE-SCALES; MEMORY HIERARCHY; NETWORKS ON CHIPS; ON-CHIP INTERCONNECTION NETWORK; PERFORMANCE; SCALE-DOWN;

NETWORK TOPOLOGY;

EID: 77952016604     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1736065.1736069     Document Type: Article

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