Virtual hierarchies to support server consolidation

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2007, Pages 46-56

  Marty, Michael R ^a   Hill, Mark D ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Cache coherence; Chip multiprocessors (CMPs); Memory hierarchies; Multicore; Partitioning; Server consolidation; Virtual machines

Indexed keywords

CACHE COHERENCE; CHIP MULTIPROCESSORS (CMP); MEMORY HIERARCHIES; SERVER CONSOLIDATION;

BUFFER STORAGE; DATA STORAGE EQUIPMENT; HIERARCHICAL SYSTEMS; PROGRAM PROCESSORS; SERVERS;

VIRTUAL REALITY;

EID: 35348900723     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1250662.1250670     Document Type: Conference Paper

References (44)

1. A. R. Alameldeen and D. A. Wood. Variability in Architectural Simulations of Multi-threaded Workloads. In Proceedings of the Ninth IEEE Symposium on High-Performance Computer Architecture, pages 7-18, Feb. 2003.
2. A. R. Alameldeen and D. A. Wood. IPC Considered Harmful for Multiprocessor Workloads. IEEE Micro, 26(4):8-17, Jul/Aug 2006.
3. AMD. AMD64 Virtualization Codenamed Pacifica Technology: Secure Virtual Machine Architecture Reference Manual, May 2005.
4. L. A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 282-293, June 2000.
5. B. M. Beckmann, M. R. Marty, and D. A. Wood. ASR: Adaptive Selective Replication for CMP Caches. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2006.
6. B. M. Beckmann and D. A. Wood. Managing Wire Delay in Large Chip-Multiprocessor Caches. In Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2004.
7. E. Bugnion, S. Devine, K. Govil, and M. Rosenblum. Disco: Running Commodity Operating Systems on Scalable Multiprocessors. ACM Transactions on Computer Systems, 15(4):319-349, 1997.
8. J. Chang and G. S. Sohi. Cooperative Caching for Chip Multiprocessors. In Proceedings of the 33nd Annual International Symposium on Computer Architecture, June 2006.
9. A. Charlesworth. Starfire: Extending the SMP Envelope. IEEE Micro, 18(1):39-49, Jan/Feb 1998.
10. D. Chiou, P. Jain, S. Devadas, and L. Rudolph. Dynamic Cache Partitioning via Columnization. In Proceedings of Design Automation Conference, 2000.
11. Z. Chishti, M. D. Powell, and T. N. Vijaykumar. Optimizing Replication, Communication, and Capacity Allocation in CMPs. In Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005.
12. S. Cho and L. Jin. Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2006.
13. A. Gupta and W.-D. Weber. Cache Invalidation Patterns in Shared-Memory Multiprocessors. IEEE Transactions on Computers, 41(7):794-810, July 1992.
14. A. Gupta, W.-D. Weber, and T. Mowry. Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes. In International Conference on Parallel Processing (ICPP), volume I, pages 312-321, 1990.
15. E. Hagersten and M. Koster. WildFire: A Scalable Path for SMPs. In Proceedings of the Fifth IEEE Symposium on High-Performance Computer Architecture, pages 172-181, Jan. 1999.
16. HP Pardoning Continuum. http://h30081.www3.hp.com/products/wlm/docs/ HPPartition.ingContinuum.pdf, June 2000.
17. L. R. Hsu, S. K. Reinhardt, R. Iyer, and S. Makineni. Communist, Utilitarian, and Capitalist Cache Policies on CMPs: Caches as a Shared Resource. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, Sept. 2006.
18. J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, and S. W. Keckler. A NUCA Substrate for Flexible CMP Cache Sharing. In Proceedings of the 19th International Conference on Supercomputing, June 2005.
19. From a Few Cores to Many: A Tera-scale Computing Research. Overview. ftp://download.intel.com/research/platform/terascale/terascale_overview_paper. pdf, 2006.
20. Intel Corporation. Intel Virtualization Technology Specifications for the IA-32 Intel Architecture, 2005.
21. R. Iyer. CQoS: A Framework for Enabling QoS in Shared. Caches of CMP Platforms. In Proceedings of the 18th International Conference on Supercomputing, pages 257-266, 2004.
22. J. Jann, L. M. Browning, and R. S. Burugula. Dynamic reconfiguration: Basic building blocks for autonomic computing on IBM pSeries servers. IBM Systems Journal, 42(1), 2003.
23. C. Kim, D. Burger, and S. W. Keckler. An Adaptive, Non-Uniform. Cache Structure for Wire-Dominated On-Chip Caches. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Oct. 2002.
24. S. Kim, D. Chandra, and Y. Solihin. Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, Sept. 2004.
25. P. Kongetira. A 32-way Multithreaded SPARC Processor. In Proceedings of the 16th HotChips Symposium, Aug. 2004.
26. J. Laudon and D. Lenoski. The SGI Origin: A ccNUMA Highly Scalable Server. In Proceedings of the 24th Annual International Symposium on Computer Architecture, pages 241-251, June 1997.
27. D. Lenoski, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 148-159, May 1990.
28. C. Liu, A. Savasubramaniam, and M. Kandemir. Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs. In Proceedings of the Tenth IEEE Symposium on High-Performance Computer Architecture, Feb. 2004.
29. M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset. Computer Architecture News, pages 92-99, Sept. 2005.
30. M. M. K. Martin, M. D. Hill, and D. A. Wood. Token Coherence: Decoupling Performance and Correctness. In Proceedings of the 30th Annual International Symposium on Computer Architecture, pages 182-193, June 2003.
31. M. R. Marty, J. D. Bingham, M. D. Hill, A. J. Hu, M. M. K. Martin, and D. A. Wood. Improving Multiple-CMP Systems Using Token Coherence. In Proceedings of the Eleventh IEEE Symposium on High-Performance Computer Architecture, Feb. 2005.
32. M. R. Marty and M. D. Hill. Coherence Ordering for Ring-based Chip Multiprocessors. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2006.
33. N. Rafique, W.-T. Lim, and M. Thottethodi. Architectural Support for Operating System-Driven CMP Cache Management. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, Sept. 2006.
34. P. Ranganathan, S. Adve, and N. P. Jouppi. Reconfigurable Caches and their Application to Media Processing. In Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000.
35. S. L. Scott. Synchronization and Communication in the Cray T3E Multiprocessor. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 26-36, Oct. 1996.
36. J. E. Smith and R. Nair. Virtual Machines. Morgan Kaufmann, 2005.
37. G. E. Suh, S. Devadas, and L. Rudolph. A. New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. In Proceedings of the Eighth IEEE Symposium on High-Performance Computer Architecture, Feb. 2002.
38. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic Cache Partitioning for CMP/SMT Systems. Journal of Supercomputing, pages 7-26, 2004.
39. J. M. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy. POWER4 System Microarchitecture. IBM Journal of Research and Development, 46(1), 2002.
40. K. Varadarajan, S. K. Nandy, V. Sharda, A. Bharadwaj, R. Iyer, S. Makineni, and D. Newell. Molecular Caches: A Caching Structure for Dynamic Creation of Application-Specific Heterogeneous Cache Regions. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2006.
41. Virtutech AB. Simics Full System Simulator, http://www.sim.ics.com/.
42. VMware. http://www.vmware.com/.
43. C. A. Waldspurger. Memory Resource Management in VMware ESX Server. In Proceedings of the 2002 Symposium on Operating Systems Design and Implementation, Dec. 2002.
44. M. Zhang and K. Asanovic. Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. In Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005.