Analysis and comparison in the energy-delay-area domain of nanometer CMOS Flip-Flops: Part I-methodology and design strategies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 5, 2011, Pages 725-736

  Alioto, Massimo ^a,b   Consoli, Elio ^c   Palumbo, Gaetano ^c  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CATANIA   (Italy)

Author keywords

Clocking; energy efficiency; energy delay tradeoff; flip flops (FFs); high speed; interconnects; leakage; Logical Effort; low power; nanometer technologies; VLSI

Indexed keywords

CLOCKING; ENERGY-DELAY TRADEOFF; FLIP-FLOPS (FFS); HIGH SPEED; INTERCONNECTS; LEAKAGE; LOGICAL EFFORT; LOW POWER; NANOMETER TECHNOLOGIES; VLSI;

FLIP FLOP CIRCUITS; TOPOLOGY;

ENERGY EFFICIENCY;

EID: 79955570855     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2041376     Document Type: Article

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