Analysis and design of low-energy flip-flops

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 52-55

  Markovic D ^a   Nikolic B ^a   Brodersen, R W ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Digital CMOS; Flip flops; Low power design; Low voltage; VLSI

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ENERGY UTILIZATION; OPTIMIZATION; PROBABILITY; VLSI CIRCUITS;

LOW-ENERGY SYSTEMS;

FLIP FLOP CIRCUITS;

EID: 0034869579     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383093     Document Type: Conference Paper

References (12)

1. Clocked storage elements
2. A 2.2W, 80 MHz superscalar RISC microprocessor
3. Clocked CMOS calculator circuitry
4. Semi-dynamic and dynamic flip-flops with embedded logic
5. Flow-through latch and edge-triggered flip-flop hybrid elements
6. Sense amplifier-based flip-flop
7. Flip-flop selection technique for power-delay trade-off
8. New clock-gating technique for low-power flip-flops
9. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
10. High-performance energy-efficient D flip-flop circuits
11. Activity-sensitive flip-flop and latch selection for reduced energy