A clock skew absorbing flip-flop

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Nedovic, Nikola ^a,b   Oklobdzija, Vojin G ^b   Walker, William W ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; PIPELINE PROCESSING SYSTEMS; TIMING DEVICES;

CLOCK SKEW; SKEW ADSORPTION; SKEW TOLERANT FLIP FLOP;

FLIP FLOP CIRCUITS;

EID: 0037969007     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. B. Nikolic, V. G. Oklobdzija, "Design and Optimization of Sense Amplifier-Based Flip-Flops," 25th ESSCIRC, pp. 410-413, 1999.
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7. Y. Takao et al, "A 0.11um CMOS Technology with Copper and Very-low-k Interconnects for High-Performance System-On-a-Chip Cores," IEDM Technical Digest, p.559-562, 2000.