A low power symmetrically pulsed dual edge-triggered flip-flop

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 399-402

  Nedovic, Nikola ^a   Walker, William W ^a   Oklobdzija, Vojin G ^b   Aleksic, Marko ^b  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; ENERGY DELAY PRODUCT; HSPICE SIMULATIONS; LOW POWER; LOW POWER APPLICATION; POWER SUPPLY VOLTAGE; STORAGE ELEMENTS;

CLOCKS; CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PRODUCT DESIGN;

FLIP FLOP CIRCUITS;

EID: 84893787373     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. N. Nedovic, M. Aleksic, V. G. Oklobdzija, "Timing Characterization of Dual-Edge Triggered Flip-Flops", Proceedings of ICCD, Austin, Texas, August 2001.
2. P. E. Gronowski et al, "A 433-MHz 64-b Quad-Issue RISC Microprocessor", IEEE Journal of Solid-State Circuits, vol. 31, no. 11, p.1687-1696, November 1996.
3. J. Tschanz et al, "Comparative Delay and Energy of Single Edge-Triggered &Dual Edge-Triggered Pulsed Flip-Flops for High Performance Microprocessors", Proceedings of ISLPED, p147-152, August 2001.
4. R. P. Llopis, M. Sachdev, "Low power, testable dual edge triggered flip-flops", ISLPED Dig. of Tech. Papers, p.341-345, 1996.
5. R. Heald et al, "A Third Generation SPARC V9 Microprocessor", IEEE Journal of Solid-State Circuits, vol. 35, no. 11, p.1526-1538, November 2000.
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7. B.A. Gieseke et al., "A 600 MHz superscalar RISC microprocessor with out-of-order execution," in ISSCC Dig. Tech. Papers, pp. 176-7, 451, Feb. 1997.
8. V. Stojanovic, V. G. Oklobdzija, "Flip-Flop", US Patent No. 6,232,810, May 15, 2001.
9. V. G. Oklobdzija, "High-Performance System Design: Circuits and Logic", IEEE Press, 1999.