Activity-sensitive flip-flop and latch selection for reduced energy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 9, 2007, Pages 1060-1064

  Heo, Seongmoo ^a   Krashinsky, Ronny ^a   Asanović, Krste ^a  

^a Department of Electrical Engineering and Computer Science   (United States)

Author keywords

Clocking; Flip flops; Latches; Low power

Indexed keywords

DATA TRANSFER; ENERGY CONSERVATION; LARGE SCALE SYSTEMS; LOGIC CIRCUITS;

CLOCKING; CYCLE TIME; PIPELINED MIPS PROCESSOR DATAPATH; SPEED REQUIREMENTS;

FLIP FLOP CIRCUITS;

EID: 34548100332     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.902211     Document Type: Article

References (19)

1. H. Partovi et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," in Dig. ISSCC, 1996, pp. 138-139.
2. H. Kawaguchi and T. Sakurai, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807-811, May 1998.
3. U. Ko and P. Balsara, "High performance, energy-efficient D flip-flop circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 1, pp. 94-98, Jan. 2000.
4. B. Kong, S. Kim, and Y. Jun, "Conditional-capture flip-flop technique for statistical power reduction," in Dig. ISSCC, 2000, pp. 290-290.
5. T. Lang, E. Musoli, and J. Cortadeira, "Individual flip-flops with gated clocks for low power datapaths," IEEE Trans. Circuits Systems II, Analog Digit. Signal Process., vol. 44, no. 6, pp. 507-516, Jun. 1997.
6. B. Nikolić V. Oklobdžija, V. Stojanović, W. Jia, J. Chiu, and M. Leung, "Improved sense-amplifier-based flip-flop: Design and measurements," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, Jun. 2000.
7. M. Nogawa and Y. Ohtomo, "A data-transition look-ahead DFF circuit for statistical reduction in power consumption," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 702-706, May 1998.
8. V. Stojanović and V. Oklobdžija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536-548, Apr. 1999.
9. A. G. M. Strollo, E. Napoli, and D. D. Caro, "New clock-gating techniques for low-power flip-flops," in Proc. ISLPED, 2000, pp. 114-119.
10. M. Hamada et al., "Flip-flop selection technique for power-delay tradeoff," in Dig. ISSCC, 1999, pp. 270-271.
11. V. Tiwari et al., "Reducing power in high-performance microprocessors," in Proc. DAC, 1998, pp. 732-737.
12. R. Gonzalez and M. Horowitz, "Energy dissipation in general purpose microprocessors," IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1277-1284, Sep. 1996.
13. J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1703-1714, Nov. 1996.
14. S. Heo and K. Asanović, "Load-sensitive flip-flop characterization," in Proc. IEEE Workshop VLSI, 2001, pp. 87-92.
15. N. P. van der Meijs and A. J. van Genderen, "Space tutorial," Delft Univ. Technol., Delft, Netherlands, Tech. Rep. ET-NT 92.22, 1992.
16. V. Zyuban and P. Kogge, "Application of STD to latch-power estimation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 7, no. 1, pp. 111-115, Jan. 1999.
17. S. Heo, R. Krashinsky, and K. Asanović, "Activity-sensitive flip-flop and latch selection for reduced energy," in Proc. 19th ARVLSI, 2001, pp. 59-74.
18. R. Krashinsky, S. Heo, M. Zhang, and K. Asanović, "SyCHOSys: Compiled energy-performance cycle simulation," in Proc. Workshop Complexity-Effective Des., 27th Int. Symp. Comput. Arch., 2000, pp. 1-10.
19. D. Bailey and B. Benschneider, "Clocking design and analysis for a 600 MHz alpha microprocessor," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1627-1633, Nov. 1998.