Design in the power-limited scaling regime

IEEE Transactions on Electron Devices

Volumn 55, Issue 1, 2008, Pages 71-83

  Nikolić, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

CMOS; Performance; Power; Technology scaling

Indexed keywords

ENERGY DISSIPATION; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; SENSITIVITY ANALYSIS;

POWER CONSTRAINTS; POWER-LIMITED SCALING; TECHNOLOGY SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 37749030900     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.911350     Document Type: Article

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