Energy optimization of pipelined digital systems using circuit sizing and supply scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 2, 2006, Pages 122-134

  Dao, Hoang Q ^a,b   Zeydel, Bart R ^a,b   Oklobdzija, Vojin G ^a,b,c  

^a IEEE   (United States)

^b University of California Davis   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuit sizing; Digital system; Energy delay characteristics; Optimal criteria; Optimization methodology; Pipelined stage; Supply voltage effects

Indexed keywords

CIRCUIT SIZING; DIGITAL SYSTEM; ENERGY-DELAY CHARACTERISTICS; OPTIMAL CRITERIA; OPTIMIZATION METHODOLOGY; PIPELINED STAGE; SUPPLY VOLTAGE EFFECTS;

NETWORKS (CIRCUITS); OPTIMIZATION; VOLTAGE CONTROL;

ENERGY UTILIZATION;

EID: 33645000007     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.863760     Document Type: Conference Paper

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