The effect of the system specification on the optimal selection of clocked storage elements

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 6, 2007, Pages 1392-1404

  Giacomotto, Christophe ^a,b   Nedovic, Nikola ^a,d   Oklobdzija, Vojin G ^a,c  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Integration Corporation   (United States)

^d FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Circuit analysis; Circuit optimization; Circuit tuning; Clocked storage elements; CMOS digital integrated circuits; Delay effects; Energy delay optimization; Energy measurement; Flip flops; Integrated circuit design; Power consumption; Registers; VLSI

Indexed keywords

CIRCUIT TUNING; CLOCKED STORAGE ELEMENTS; DELAY EFFECTS; ENERGY DELAY OPTIMIZATION; INTEGRATED CIRCUIT DESIGN;

ELECTRIC POWER MEASUREMENT; ELECTRIC POWER UTILIZATION; FLIP FLOP CIRCUITS; OPTIMIZATION; SOLID STATE DEVICE STRUCTURES; TOPOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 34249777840     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.896516     Document Type: Article

References (23)

1. V. Stojanovic and V. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536-548, Apr. 1999.
2. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic, and N. M. Nedovic, Digital System Clocking: High-Performance and Low-Power Aspects, 1st ed. New York: Wiley/IEEE Press, 2003.
3. V. G. Oklobdzija, "Clocking and clocked storage elements in a multi-gigahertz environment," IBM J. Res. Devel., vol. 47, pp. 567-584, Sep./ Nov. 2003.
4. J. Tschanz, S. Narendra, C. Zhanping, S. Borkar, M. Sachdev, and V. De, "Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors," in Proc. Int. Symp. Low Power Electronics and Design (ISLPED), 2001, pp. 147-152.
5. N. Nedovic, "Clocked storage elements for high-performance applications,"Ph.D. dissertation, University of California, Davis, 2003, p. 353.
6. N. Nedovic. W. W. Walker, and V. G. Oklobdzija. "A test circuit for measurement of clocked storage element characteristics," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1294-1304, Aug. 2004.
7. V. Zyuban, "Optimization of scannable latches for low energy," IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 11, no. 10, pp. 778-788, Oct. 2003.
8. D. Markovic. B. Nikolic, and R. W. Brodersen, "Analysis and design of low-energy flip-flops," in Proc. Int. Symp. Low Power Electronics and Design (ISLPED), 2001, pp. 52-55.
9. V. Zyuban D. Brooks, V. Srinivasan, M. Gschwind, and P. BoseP. N. StrenskiP. G. Emma, "Integrated analysis of power and performance for pipelined microprocessors," IEEE Tians. Comput., vol. 53, no. 8, pp. 1004-1016, Aug. 2004.
10. V. Zyuban and P. Strenski, "Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels," in Proc. Int. Symp. Low Power Electronics and Design (ISLPED), 2002, pp. 166-171.
11. S. Heo and K. Asanovic, "Load-sensitive flip-flop characterizations," in Proc. IEEE Computer Society Workshop on VLSI, 2001. pp. 87-92.
12. H. Q. DaoB. R. ZeydelV. G. Oklobdzija, "Energy optimization of pipelined digital systems using circuit sizing and supply scaling," IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 14, no. 2, pp. 122-134, Feb. 2006.
13. R. Heald et al., "A third-generation SPARC V9 64-b microprocessor," IEEE J. Solid-State Circuits, vol. 35. no. 11, pp. 1526-1538, Nov. 2000.
14. I. E. Sutherland and R. F. Sproull, Logical Effort: Designing for Speed on the Back of an Envelope. Cambridge, MA: MIT Press, 1991.
15. P. M. Kogge and H. S. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations," IEEE Trans. Comput., vol. C-22, pp. 786-793, Aug. 1973.
16. F. Klass, "Semi-dynamic and dynamic flip-flops with embedded logic," in Proc. Symp. VLSI Circuits, 1998, pp. 108-109.
17. J. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 62-70, Feb. 1989.
18. N. NedovicV. G. OklobdzijaW. W. Walker, "A clock skew absorbing flip-flop," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 342-352.
19. S. D. Naffziger and G. Hammond, "The implementation of the next-generation 64 b Itanium microprocessor," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 344-472.
20. G. Gerosa et al., "A 2.2 W, 80 MHz superscalar RISC microprocessor," IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1440-1454, Dec. 1994.
21. D. Markovic and J. Tschanz, "Transmission-gate based flip-flop," U.S. patent 6,642,765, Nov. 2003.
22. Y. SuzukiK. OdagawaT. Abe, "Clocked CMOS calculator circuitry," IEEE J. Solid-State Circuits, vol. SC-8, no. 6, pp. 462-469, Dec. 1973.
23. C. Giacomotto and N. NedovicV. G. Oklobdzija, "Energy-delay space analysis for clocked storage elements under process variations," in Proc. 16th Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France, 2006, pp. 360-369.