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Volumn 34, Issue 4, 1999, Pages 536-548

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY;

EID: 0033116422     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.753687     Document Type: Article
Times cited : (515)

References (16)
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  • 2
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    • An enhanced power meter for SPICE2 circuit simulation
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    • _, "Principle of CMOS circuit power-delay optimization with transistor sizing," in Proc. Int. Symp. Circuits and Systems (ISCAS'96), 1996, vol. 1, pp. 62-69.
    • (1996) Proc. Int. Symp. Circuits and Systems (ISCAS'96) , vol.1 , pp. 62-69
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    • New single-clock CMOS latches and flipflops with improved speed and power savings
    • Jan.
    • _, "New single-clock CMOS latches and flipflops with improved speed and power savings," IEEE J. Solid-State Circuits, vol. 32, Jan. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32
  • 6
    • 0031258487 scopus 로고    scopus 로고
    • Comments on new single-clock CMOS latches and flipflops with improved speed and power savings
    • Oct.
    • G. M. Blair, "Comments on new single-clock CMOS latches and flipflops with improved speed and power savings," IEEE J. Solid-State Circuits, vol. 32, pp. 1610-1611, Oct. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , pp. 1610-1611
    • Blair, G.M.1
  • 14
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    • Design techniques for high-performance, energy-efficient control logic
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    • U. Ko, A. Hill, and P. T. Balsara, "Design techniques for high-performance, energy-efficient control logic," in ISLPED Dig. Tech. Papers, Aug. 1996.
    • (1996) ISLPED Dig. Tech. Papers
    • Ko, U.1    Hill, A.2    Balsara, P.T.3
  • 15
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    • Latches and flip-flops for low power systems
    • A. Chandrakasan and R. Brodersen, Eds. Piscataway, NJ: IEEE Press
    • C. Svensson and J. Yuan, "Latches and flip-flops for low power systems," in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Eds. Piscataway, NJ: IEEE Press, 1998, pp. 233-238.
    • (1998) Low Power CMOS Design , pp. 233-238
    • Svensson, C.1    Yuan, J.2
  • 16
    • 0031640603 scopus 로고    scopus 로고
    • Semi-dynamic and dynamic flip-flops with embedded logic
    • Honolulu, HI, June 11-13
    • F. Klass, "Semi-dynamic and dynamic flip-flops with embedded logic," in 1998 Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, June 11-13, 1998, pp. 108-109.
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    • Klass, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.