Variable sampling window flip-flops for low-power high-speed VLSI

IEE Proceedings: Circuits, Devices and Systems

Volumn 152, Issue 3, 2005, Pages 266-271

  Shin, S D ^a   Kong, B S ^b  

^a Hankuk Aviation University   (South Korea)

^b Sungkyunkwan University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; FLIP FLOP CIRCUITS; SHORT CIRCUIT CURRENTS;

CONDITIONAL-CAPTURE FLIP-FLOP (CCFF); DATA LATCHING; HYBRID LATCH FLIP-FLOP (HLFF); POWER DISSIPATION;

VLSI CIRCUITS;

EID: 23744447698     PISSN: 13502409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cds:20040789     Document Type: Conference Paper

References (11)

1. Weste, N., and Eshragian, K.: 'Principles of CMOS VLSI design: a systems perspective' (Addison-Wesley, Reading, MA, USA, 1986), pp. 145-149
2. Labaey, J.M. et al.: 'Low power design methodologies' (Kluwer Academic, Norwell, MA, USA, 1996)
3. Stojanovic, V., and Oklobdzija, V.G.: 'Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems', IEEE J. Solid-State Circuits, 1999, 34, (4), pp. 536-548
4. Partovi, H., Burd, R., Salim, U., Wever, F., DiGregprio., L., and Draper, D.: 'Flow-through latch and edge-triggered nip-flop hybrid elements'. Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, CA, USA, 1996, pp. 138-139
5. Klass, F.: 'Semi-dynamic and dynamic flip-flops with embedded logic'. IEEE Symp. on VLSI circuits, Digest of Technical Papers, June 1998, pp. 108-109
6. Nikolic, B., Oklobdzija, V.G., Stojanovic, V., Jia, W., Chiu, J.K.-S., and Lung, M.M.-T.: 'Improved sense amplifier-based flip-flop: design and measurements,', IEEE J. Solid-State Circuits, 2000, 35, (6), pp. 876-884
7. Kong, B.-S., Kim, S.-S., and Jun, Y.-H.: 'Conditional-capture flip-flop for statistical power reduction,', IEEE J. Solid-State Circuits, 2001, 36, (8), pp. 1263-1271
8. Kawaguchi, H., and Sakurai, T.: 'A reduced clock-swing flip-flop (RCSFF) for 63% power reduction', IEEE J. Solid-State Circuits, 1998, 33, (5), pp. 807-811
9. Mishra, S.M., Rofail, S.S., and Yeo, K.-S.: 'A high performance double edge-triggered flip-flop using a merged feedback technique', IEE Proc., Circuits Devices Syst., 2000, 147 (6), pp. 363-368
10. Mishra, S.M. et al.: 'A high performance double edge-triggered flip-flops', IEE Proc., Circuits Devices Syst., 2000, 147, (5), pp. 283-290
11. Shin, S.-D., Choi, H., and Kong, B.-S.: 'Variable sampling window flip-flop for low-power application.'. IEEE Int. Symp. on Circuits and Systems, Digest of Technical Papers, Bangkok, Thailand, 2003, pp. 257-260