Low power, testable dual edge triggered flip-flops

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1996, Pages 341-345

  Llopis, Rafael Peset ^a   Sachdev, Manoj ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; POWER ELECTRONICS; TIMING CIRCUITS; TRIGGER CIRCUITS; VLSI CIRCUITS;

CLOCK NETWORK; PROPAGATION DELAY;

FLIP FLOP CIRCUITS;

EID: 0030386692     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)